Datasheet Summary
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PRELIMINARY
CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18
72-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
Features
- Configurations
With Read Cycle Latency of 2.5 cycles: CY7C2561KV18
- 8M x 8 CY7C2576KV18
- 8M x 9 CY7C2563KV18
- 4M x 18 CY7C2565KV18
- 2M x 36
Separate independent read and write data ports
- Supports concurrent transactions 550 MHz clock for high bandwidth 4-word burst for reducing address bus frequency Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MHz Available in 2.5 clock cycle latency Two input clocks (K and K) for precise DDR timing
- SRAM uses...