CY7C2563KV18
Features
- Configurations
With Read Cycle Latency of 2.5 cycles: CY7C2561KV18
- 8M x 8 CY7C2576KV18
- 8M x 9 CY7C2563KV18
- 4M x 18 CY7C2565KV18
- 2M x 36
Separate independent read and write data ports
- Supports concurrent transactions 550 MHz clock for high bandwidth 4-word burst for reducing address bus frequency Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MHz Available in 2.5 clock cycle latency Two input clocks (K and K) for precise DDR timing
- SRAM uses rising edges only Echo clocks (CQ and CQ) simplify data capture in high-speed systems Data valid pin (QVLD) to indicate valid data on the output On-Die Termination (ODT) feature
- Supported for D[x:0], BWS[x:0], and K/K inputs Single multiplexed address input bus latches address inputs for read and write ports Separate port selects for depth expansion Synchronous internally self-timed writes QDR™-II+ operates with 2.5 cycle read latency when DOFF is asserted HIGH...
