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CY7C2270KV18 - 36-Mbit DDR II+ SRAM Two-Word Burst Architecture

Download the CY7C2270KV18 datasheet PDF. This datasheet also covers the CY7C2268KV18 variant, as both devices belong to the same 36-mbit ddr ii+ sram two-word burst architecture family and are provided as variant models within a single manufacturer datasheet.

Features

  • 36-Mbit density (2 M × 18, 1 M × 36).
  • 550 MHz clock for high bandwidth.
  • Two-word burst for reducing address bus frequency.
  • Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz.
  • Available in 2.5 clock cycle latency.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Echo clocks (CQ and CQ) simplify data capture in high speed systems.
  • Data valid pin (QVLD) to indicate valid data on the output.
  • On.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C2268KV18-CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C2245KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture
CY7C225A 512 x 8 Registered PROM
CY7C2262XV18 36-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture
CY7C2263KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture
CY7C2263XV18 36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CY7C2268KV18/CY7C2270KV18 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features ■ 36-Mbit density (2 M × 18, 1 M × 36) ■ 550 MHz clock for high bandwidth ■ Two-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz ■ Available in 2.
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