CY7C2265XV18 Datasheet 36-mbit Qdr Ii+ Xtreme Sram Four-word Burst Architecture

Manufacturer: Cypress (now Infineon)

Overview: CY7C2263XV18 CY7C2265XV18 36-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 36-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.

This datasheet includes multiple variants, all published together in a single manufacturer document.

Datasheet Details

Part number	CY7C2265XV18
Manufacturer	Cypress (now Infineon)
File Size	1.07 MB
Description	36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture
Datasheet	CY7C2265XV18 CY7C2263XV18 Datasheet (PDF)

Key Features

Separate independent read and write data ports.
Supports concurrent transactions.
633 MHz clock for high bandwidth.
Four-word burst for reducing address bus frequency.
Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 1266 MHz) at 633 MHz.
Available in 2.5 clock cycle latency.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Echo clocks (CQ and CQ) simplify data capture in high-speed sy.

CY7C2265XV18 Distributor

More Datasheets from Cypress (now Infineon)

Part Number	Description
CY7C2265KV18	36-Mbit QDR II+ SRAM Four-Word Burst Architecture
CY7C2262XV18	36-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture
CY7C2263KV18	36-Mbit QDR II+ SRAM Four-Word Burst Architecture
CY7C2263XV18	36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture
CY7C2264XV18	36-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture
CY7C2268KV18	36-Mbit DDR II+ SRAM Two-Word Burst Architecture
CY7C2245KV18	36-Mbit QDR II+ SRAM Four-Word Burst Architecture
CY7C225A	512 x 8 Registered PROM
CY7C2270KV18	36-Mbit DDR II+ SRAM Two-Word Burst Architecture
CY7C2163KV18	18-Mbit QDR II+ SRAM Four-Word Burst Architecture