This page provides the datasheet information for the CY7C2265XV18, a member of the CY7C2263XV18 36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture family.
Datasheet Summary
Features
Separate independent read and write data ports.
Supports concurrent transactions.
633 MHz clock for high bandwidth.
Four-word burst for reducing address bus frequency.
Double Data Rate (DDR) interfaces on both read and write ports
(data transferred at 1266 MHz) at 633 MHz.
Available in 2.5 clock cycle latency.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Echo clocks (CQ and CQ) simplify data capture in high-speed
sy.
CY7C2263XV18 CY7C2265XV18
36-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
36-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
Features
■ Separate independent read and write data ports ❐ Supports concurrent transactions
■ 633 MHz clock for high bandwidth ■ Four-word burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces on both read and write ports
(data transferred at 1266 MHz) at 633 MHz ■ Available in 2.
CY7C2265XV18 Datasheet
