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CY7C2265XV18

The CY7C2265XV18 is 36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture designed by Cypress Semiconductor.

Product Overview

Cypress Semiconductor

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CY7C2265XV18 36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture by Cypress Semiconductor - Datasheet Preview — Datasheet preview – CY7C2265XV18

Datasheet Details

Part number	CY7C2265XV18, CY7C2263XV18
Manufacturer	Cypress Semiconductor
File Size	1.07 MB
Description	36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture
Datasheet	CY7C2263XV18-CypressSemiconductor.pdf
Note	This datasheet PDF includes multiple part numbers: CY7C2265XV18, CY7C2263XV18. Please refer to the document for exact specifications by model.
Additional preview pages of the CY7C2265XV18 datasheet.

Product details

Features

Separate independent read and write data ports.
Supports concurrent transactions.
633 MHz clock for high bandwidth.
Four-word burst for reducing address bus frequency.
Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 1266 MHz) at 633 MHz.
Available in 2.5 clock cycle latency.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Echo clocks (CQ and CQ) simplify data capture in high-speed sy.

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Other Datasheets by Cypress Semiconductor

CY7C2265KV18 - 36-Mbit QDR II+ SRAM Four-Word Burst Architecture
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CY7C2263KV18 - 36-Mbit QDR II+ SRAM Four-Word Burst Architecture
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Published: Mar 14, 2017 |