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CY7C2170KV18 - 18-Mbit DDR II+ SRAM Two-Word Burst Architecture

Download the CY7C2170KV18 datasheet PDF. This datasheet also covers the CY7C2168KV18 variant, as both devices belong to the same 18-mbit ddr ii+ sram two-word burst architecture family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • 18-Mbit density (1M × 18, 512K × 36).
  • 550-MHz clock for high bandwidth.
  • Two-word burst for reducing address bus frequency.
  • Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz.
  • Available in 2.5 clock cycle latency.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Echo clocks (CQ and CQ) simplify data capture in high-speed systems.
  • Data valid pin (QVLD) to indicate valid data on the output.
  • On.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C2168KV18-CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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CY7C008V 3.3V 64K/128K x 8/9 Dual-Port Static RAM Cypress
CY7C009 64K/128K x 8/9 Dual-Port Static RAM Cypress

Other Datasheets by Cypress (now Infineon)

Part Number Description
CY7C2163KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture
CY7C2165KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture
CY7C2168KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture
CY7C2245KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture
CY7C225A 512 x 8 Registered PROM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CY7C2168KV18/CY7C2170KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features ■ 18-Mbit density (1M × 18, 512K × 36) ■ 550-MHz clock for high bandwidth ■ Two-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz ■ Available in 2.