CY7C2168KV18 Overview
Key Specifications
Package: FBGA
Mount Type: Surface Mount
Pins: 165
Operating Voltage: 1.8 V
Key Features
- 550-MHz clock for high bandwidth
- Two-word burst for reducing address bus frequency
- Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz
- Available in 2.5 clock cycle latency
- Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only
- Echo clocks (CQ and CQ) simplify data capture in high-speed systems
- Data valid pin (QVLD) to indicate valid data on the output
- On-die termination (ODT) feature ❐ Supported for D[x:0], BWS[x:0], and K/K inputs
- Synchronous internally self-timed writes
- DDR II+ operates with 2.5 cycle read latency when DOFF is asserted HIGH
