CY7C2168KV18 - 18-Mbit DDR II+ SRAM Two-Word Burst Architecture

Features

18-Mbit density (1M × 18, 512K × 36).
550-MHz clock for high bandwidth.
Two-word burst for reducing address bus frequency.
Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz.
Available in 2.5 clock cycle latency.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Echo clocks (CQ and CQ) simplify data capture in high-speed systems.
Data valid pin (QVLD) to indicate valid data on the output.
On.

Cypress Semiconductor

Datasheet Details

Part number	CY7C2168KV18
Manufacturer	Cypress
File Size	624.09 KB
Description	18-Mbit DDR II+ SRAM Two-Word Burst Architecture
Datasheet	CY7C2168KV18 Datasheet
Additional preview pages of the CY7C2168KV18 datasheet.

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Full PDF Text Transcription

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CY7C2168KV18/CY7C2170KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features ■ 18-Mbit density (1M × 18, 512K × 36) ■ 550-MHz clock for high bandwidth ■ Two-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz ■ Available in 2.

Published: Mar 14, 2017 |