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CY7C1992BV18 Datasheet 1.8V Synchronous Pipelined SRAM

Manufacturer: Cypress (now Infineon)

Download the CY7C1992BV18 datasheet PDF. This datasheet also includes the CY7C1392BV18 variant, as both parts are published together in a single manufacturer document.

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Note: The manufacturer provides a single datasheet file (CY7C1392BV18-CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

Overview

CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 18-Mbit DDR-II SIO SRAM 2-Word Burst.

Key Features

  • 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36).
  • 300 MHz clock for high bandwidth.
  • 2-word burst for reducing address bus frequency.
  • Double Data Rate (DDR) interfaces (data transferred at 600 MHz) at 300 MHz.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
  • Echo clocks (CQ and CQ) simplify data capture in high-speed systems.

More Datasheets from Cypress (now Infineon)

Part Number Description
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CY7C199D 256K (32K x 8) Static RAM
CY7C199N 32K x 8 Static RAM
CY7C190 (CY7C190 / CY7C189) 16 x 4 Static R/W RAM
CY7C1910BV18 1.8V Synchronous Pipelined SRAM
CY7C1911BV18 (CY7C1x1xBV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
CY7C1911CV18 (CY7C1x1xCV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
CY7C1911JV18 (CY7C1x1xJV18) 18-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C1911KV18 18-Mbit QDR II SRAM Four-Word Burst Architecture