CY7C1992BV18 Overview
CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture.
CY7C1992BV18 Key Features
- 300 MHz clock for high bandwidth
- 2-word burst for reducing address bus frequency
- Double Data Rate (DDR) interfaces
- Two input clocks (K and K) for precise DDR timing
- SRAM uses rising edges only
- Two input clocks for output data (C and C) to minimize clock
- Echo clocks (CQ and CQ) simplify data capture in high-speed
- Synchronous internally self-timed writes
- 1.8V core power supply with HSTL inputs and outputs
- Variable drive HSTL output buffers