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Cypress Semiconductor Electronic Components Datasheet

CY7C1992BV18 Datasheet

1.8V Synchronous Pipelined SRAM

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CY7C1392BV18, CY7C1992BV18
CY7C1393BV18, CY7C1394BV18
18-Mbit DDR-II SIO SRAM 2-Word
Burst Architecture
Features
18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)
300 MHz clock for high bandwidth
2-word burst for reducing address bus frequency
Double Data Rate (DDR) interfaces
(data transferred at 600 MHz) at 300 MHz
Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
Synchronous internally self-timed writes
1.8V core power supply with HSTL inputs and outputs
Variable drive HSTL output buffers
Expanded HSTL output voltage (1.4V–VDD)
Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)
Offered in both Pb-free and non Pb-free packages
JTAG 1149.1 compatible test access port
Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1392BV18 – 2M x 8
CY7C1992BV18 – 2M x 9
CY7C1393BV18 – 1M x 18
CY7C1394BV18 – 512K x 36
Functional Description
The CY7C1392BV18, CY7C1992BV18, CY7C1393BV18, and
CY7C1394BV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with Double Data Rate Separate IO (DDR-II SIO)
architecture. The DDR-II SIO consists of two separate ports: the
read port and the write port to access the memory array. The
read port has data outputs to support read operations and the
write port has data inputs to support write operations. The DDR-II
SIO has separate data inputs and data outputs to completely
eliminate the need to “turn-around” the data bus required with
common IO devices. Access to each port is accomplished
through a common address bus. Addresses for read and write
are latched on alternate rising edges of the input (K) clock. Write
data is registered on the rising edges of both K and K. Read data
is driven on the rising edges of C and C if provided, or on the
rising edge of K and K if C/C are not provided. Each address
location is associated with two 8-bit words in the case of
CY7C1392BV18, two 9-bit words in the case of
CY7C1992BV18, two 18-bit words in the case of
CY7C1393BV18, and two 36-bit words in the case of
CY7C1394BV18 that burst sequentially into or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs are tightly matched to the
two output echo clocks CQ/CQ, eliminating the need to capture
data separately from each individual DDR-II SIO SRAM in the
system design. Output data clocks (C/C) enable maximum
system clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Selection Guide
Description
Maximum Operating Frequency
Maximum Operating Current
300 MHz
300
x8 820
x9 825
x18 865
x36 935
278 MHz
278
770
775
800
850
250 MHz
250
700
700
725
770
200 MHz
200
575
575
600
630
167 MHz
167
485
490
500
540
Unit
MHz
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-05623 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 2, 2008
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Cypress Semiconductor Electronic Components Datasheet

CY7C1992BV18 Datasheet

1.8V Synchronous Pipelined SRAM

No Preview Available !

CY7C1392BV18, CY7C1992BV18
CY7C1393BV18, CY7C1394BV18
Logic Block Diagram (CY7C1392BV18)
D[7:0]
8
A(19:0) 20
Address
Register
K
K
DOFF
CLK
Gen.
R/W
VREF
LD
NWS[1:0]
Control
Logic
Write
Write
Data Reg Data Reg
Read Data Reg.
16
8
8
Control
Logic
LD
R/W
C
C
Reg.
Reg.
Reg. 8
8
8
CQ
CQ
Q[7:0]
Logic Block Diagram (CY7C1992BV18)
D[8:0]
9
A(19:0) 20
Address
Register
K
K
DOFF
R/W
VREF
LD
BWS[0]
CLK
Gen.
Control
Logic
Write
Write
Data Reg Data Reg
Read Data Reg.
18
9
9
Control
Logic
LD
R/W
C
C
Reg.
Reg.
Reg. 9
9
9
CQ
CQ
Q[8:0]
Document #: 38-05623 Rev. *D
Page 2 of 31
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Part Number CY7C1992BV18
Description 1.8V Synchronous Pipelined SRAM
Maker Cypress Semiconductor
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