CY7C1916BV18 - 18-Mbit DDR-II SRAM 2-Word Burst Architecture

Product Overview

Cypress Semiconductor

Part number	CY7C1916BV18
Manufacturer	Cypress Semiconductor
File Size	551.73 KB
Description	18-Mbit DDR-II SRAM 2-Word Burst Architecture
Datasheet	CY7C1916BV18 Datasheet
Note	This datasheet PDF includes multiple part numbers: CY7C1916BV18, CY7C1316BV18. Please refer to the document for exact specifications by model.
Additional preview pages of the CY7C1916BV18 datasheet.

The CY7C1316BV18, CY7C1916BV18, CY7C1318BV18, and CY7C1320BV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II architecture.

18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36).
300-MHz clock for high bandwidth.
2-Word burst for reducing address bus frequency.
Double Data Rate (DDR) interfaces (data transferred at 600 MHz) @ 300 MHz.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches.
Echo clocks (CQ and CQ) simplify data cap.

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Published: Apr 15, 2011 |