CY7C1916BV18
Overview
- 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)
- 300-MHz clock for high bandwidth
- 2-Word burst for reducing address bus frequency
- Double Data Rate (DDR) interfaces (data transferred at 600 MHz) @ 300 MHz
- Two input clocks (K and K) for precise DDR timing - SRAM uses rising edges only
- Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches
- Echo clocks (CQ and CQ) simplify data capture in high-speed systems
- Synchronous internally self-timed writes
- 1.8V core power supply with HSTL inputs and outputs
- Variable drive HSTL output buffers
