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CY7C1910BV18 Datasheet 1.8V Synchronous Pipelined SRAM

Manufacturer: Cypress (now Infineon)

Download the CY7C1910BV18 datasheet PDF. This datasheet also includes the CY7C1310BV18 variant, as both parts are published together in a single manufacturer document.

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Note: The manufacturer provides a single datasheet file (CY7C1310BV18-CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

Overview

CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 18-Mbit QDR™-II SRAM 2-Word Burst.

Key Features

  • Separate independent read and write data ports.
  • Supports concurrent transactions.
  • 250 MHz clock for high bandwidth.
  • 2-word burst on all accesses.
  • Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 500 MHz) at 250 MHz.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
  • Echo clocks (CQ and CQ) simp.

More Datasheets from Cypress (now Infineon)

Part Number Description
CY7C1911BV18 (CY7C1x1xBV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
CY7C1911CV18 (CY7C1x1xCV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
CY7C1911JV18 (CY7C1x1xJV18) 18-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C1911KV18 18-Mbit QDR II SRAM Four-Word Burst Architecture
CY7C1916BV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1916CV18 (CY7C1xxxCV18) 18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1916JV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1916KV18 18-Mbit DDR II SRAM Two-Word Burst Architecture
CY7C1917BV18 1.8V Synchronous Pipelined SRAM
CY7C191xBV18 (CY7C1xxxxVxx) RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata