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CY7C1911BV18 Datasheet (CY7C1x1xBV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture

Manufacturer: Cypress (now Infineon)

Download the CY7C1911BV18 datasheet PDF. This datasheet also includes the CY7C1311BV18 variant, as both parts are published together in a single manufacturer document.

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Note: The manufacturer provides a single datasheet file (CY7C1311BV18_CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

General Description

The CY7C1311BV18, CY7C1911BV18, CY7C1313BV18, and CY7C1315BV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture.

QDR-II architecture consists of two separate ports to access the memory array.

The Read port has dedicated Data Outputs to support Read operations and the Write port has dedicated Data Inputs to support Write operations.

Overview

CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit QDR™-II SRAM 4-Word Burst.

Key Features

  • Separate Independent Read and Write data ports.
  • Supports concurrent transactions.
  • 300-MHz clock for high bandwidth.
  • 4-Word Burst for reducing address bus frequency.
  • Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 600 MHz) at 300 MHz.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Two input clocks for output data (C and C) to minimize clock-skew and flight-.

More Datasheets from Cypress (now Infineon)

Part Number Description
CY7C1911CV18 (CY7C1x1xCV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
CY7C1911JV18 (CY7C1x1xJV18) 18-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C1911KV18 18-Mbit QDR II SRAM Four-Word Burst Architecture
CY7C1910BV18 1.8V Synchronous Pipelined SRAM
CY7C1916BV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1916CV18 (CY7C1xxxCV18) 18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1916JV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1916KV18 18-Mbit DDR II SRAM Two-Word Burst Architecture
CY7C1917BV18 1.8V Synchronous Pipelined SRAM
CY7C191xBV18 (CY7C1xxxxVxx) RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata