CY7C1650KV18 Datasheet 144-mbit Ddr Ii+ Sram Two-word Burst Architecture

Manufacturer: Cypress (now Infineon)

Overview: CY7C1648KV18 CY7C1650KV18 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.

This datasheet includes multiple variants, all published together in a single manufacturer document.

Datasheet Details

Part number	CY7C1650KV18
Manufacturer	Cypress (now Infineon)
File Size	597.87 KB
Description	144-Mbit DDR II+ SRAM Two-Word Burst Architecture
Datasheet	CY7C1650KV18 CY7C1648KV18 Datasheet (PDF)

Key Features

144-Mbit density (8 M × 18, 4 M × 36).
450-MHz clock for high bandwidth.
Two-word burst for reducing address bus frequency.
Double data rate (DDR) interfaces (data transferred at 900 MHz) at 450 MHz.
Available in 2.0-clock cycle latency.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Echo clocks (CQ and CQ) simplify data capture in high-speed systems.
Data valid pin (QVLD) to indicate valid data on the output.
Sy.

CY7C1650KV18 Distributor

More Datasheets from Cypress (now Infineon)

Part Number	Description
CY7C1612KV18	144-Mbit QDR II SRAM Two-Word Burst Architecture
CY7C1613KV18	144-Mbit QDR II SRAM Four-Word Burst Architecture
CY7C1614KV18	144-Mbit QDR II SRAM Two-Word Burst Architecture
CY7C1615KV18	144-Mbit QDR II SRAM Four-Word Burst Architecture
CY7C1618KV18	144-Mbit DDR II SRAM Two-Word Burst Architecture
CY7C1620KV18	144-Mbit DDR II SRAM Two-Word Burst Architecture
CY7C1625KV18	144-Mbit QDR II SRAM Two-Word Burst Architecture
CY7C164	16K x 4 Static RAM
CY7C1643KV18	144-Mbit QDR II+ SRAM Four-Word Burst Architecture
CY7C1645KV18	144-Mbit QDR II+ SRAM Four-Word Burst Architecture