This page provides the datasheet information for the CY7C1650KV18, a member of the CY7C1648KV18 144-Mbit DDR II+ SRAM Two-Word Burst Architecture family.
Datasheet Summary
Features
144-Mbit density (8 M × 18, 4 M × 36).
450-MHz clock for high bandwidth.
Two-word burst for reducing address bus frequency.
Double data rate (DDR) interfaces (data transferred at
900 MHz) at 450 MHz.
Available in 2.0-clock cycle latency.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Echo clocks (CQ and CQ) simplify data capture in high-speed
systems.
Data valid pin (QVLD) to indicate valid data on the output.
CY7C1648KV18 CY7C1650KV18
144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)
144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)
Features
■ 144-Mbit density (8 M × 18, 4 M × 36) ■ 450-MHz clock for high bandwidth ■ Two-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces (data transferred at
900 MHz) at 450 MHz ■ Available in 2.0-clock cycle latency ■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only ■ Echo clocks (CQ and CQ) simplify data capture in high-speed
systems ■ Data valid pin (QVLD) to indicate valid data on the output ■ Synchronous internally self-timed writes ■ DDR II+ operates with 2.
CY7C1650KV18 Datasheet
