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CY7C1648KV18 - 144-Mbit DDR II+ SRAM Two-Word Burst Architecture

Cypress Semiconductor

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Datasheet Details

Part number: CY7C1648KV18
Manufacturer: Cypress Semiconductor
File Size: 597.87 KB
Datasheet: CY7C1648KV18-CypressSemiconductor.pdf
Description: 144-Mbit DDR II+ SRAM Two-Word Burst Architecture

CY7C1648KV18 Product details

Features

144-Mbit density (8 M × 18, 4 M × 36).
450-MHz clock for high bandwidth.
Two-word burst for reducing address bus frequency.
Double data rate (DDR) interfaces (data transferred at 900 MHz) at 450 MHz.
Available in 2.0-clock cycle latency.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Echo clocks (CQ and CQ) simplify data capture in high-speed systems.
Data valid pin (QVLD) to indicate valid data on the output.
Sy.

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144-Mbit DDR II + SRAM Two-Word Burst Architecture Cypress Semiconductor

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