CY7C1618KV18 - 144-Mbit DDR II SRAM Two-Word Burst Architecture

Cypress Semiconductor

Datasheet Details

144-Mbit density (8M × 18, 4M × 36).
333 MHz clock for high bandwidth.
Two-word burst for reducing address bus frequency.
Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
Echo clocks (CQ and CQ) simplify data capture in high-speed systems.
Synchronous i.

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