CY7C1613KV18
Overview
- Separate independent read and write data ports ❐ Supports concurrent transactions
- 333 MHz clock for high bandwidth
- Four-word burst for reducing address bus frequency
- Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz
- Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only
- Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
- Echo clocks (CQ and CQ) simplify data capture in high speed systems
- Single multiplexed address input bus latches address inputs for read and write ports
- Separate port selects for depth expansion
- Synchronous internally self-timed writes
