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CY7C15632KV18 Datasheet

72-Mbit QDR II+ SRAM Four-Word Burst Architecture

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CY7C15632KV18
72-Mbit QDR® II+ SRAM Four-Word
Burst Architecture (2.5 Cycle Read Latency)
72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)
Features
Separate Independent Read and Write Data Ports
Supports concurrent transactions
500 MHz Clock for High Bandwidth
Four-word Burst for Reducing Address Bus Frequency
Double Data Rate (DDR) Interfaces on both Read and Write
Ports (data transferred at 1000 MHz) at 500 MHz
Available in 2.5 Clock Cycle Latency
Two Input Clocks (K and K) for precise DDR Timing
SRAM uses rising edges only
Echo Clocks (CQ and CQ) simplify Data Capture in High Speed
Systems
Data Valid Pin (QVLD) to indicate Valid Data on the Output
Single Multiplexed Address Input Bus latches Address Inputs
for Read and Write Ports
Separate Port selects for Depth Expansion
Synchronous Internally Self-timed Writes
QDR® II+ operates with 2.5 cycle read latency when DOFF is
asserted HIGH
Operates similar to QDR I Device with one Cycle Read Latency
when DOFF is asserted LOW
Available in × 18 Configuration
Full Data Coherency, providing Most Current Data
Core VDD = 1.8 V ± 0.1 V; I/O VDDQ = 1.4 V to VDD [1]
Supports both 1.5 V and 1.8 V I/O supply
HSTL Inputs and Variable Drive HSTL Output Buffers
Available in 165-ball FBGA Package (13 × 15 × 1.4 mm)
Offered in both Pb-free and non Pb-free Packages
JTAG 1149.1 compatible Test Access Port
Phase-Locked Loop (PLL) for Accurate Data Placement
Configurations
With Read Cycle Latency of 2.5 cycles:
CY7C15632KV18 – 4 M × 18
Functional Description
The CY7C15632KV18 is a 1.8 V Synchronous Pipelined SRAM,
equipped with QDR II+ architecture. Similar to QDR II
architecture, QDR II+ architecture consists of two separate ports:
the read port and the write port to access the memory array. The
read port has dedicated data outputs to support read operations
and the write port has dedicated data inputs to support write
operations. QDR II+ architecture has separate data inputs and
data outputs to completely eliminate the need to “turnaround” the
data bus that exists with common I/O devices. Each port is
accessed through a common address bus. Addresses for read
and write addresses are latched on alternate rising edges of the
input (K) clock. Accesses to the QDR II+ read and write ports are
completely independent of one another. To maximize data
throughput, both read and write ports are equipped with DDR
interfaces. Each address location is associated with four 18-bit
words that burst sequentially into or out of the device. Because
data is transferred into and out of the device on every rising edge
of both input clocks (K and K), memory bandwidth is maximized
while simplifying system design by eliminating bus
“turnarounds”.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
For a complete list of related documentation, click here.
Selection Guide
Maximum Operating Frequency
Maximum Operating Current
Description
500 MHz 450 MHz 400 MHz Unit
500 450 400 MHz
× 18 850 780 710 mA
Note
1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support VDDQ = 1.4 V to VDD.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-54932 Rev. *K
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 9, 2015


Cypress Semiconductor Electronic Components Datasheet

CY7C15632KV18 Datasheet

72-Mbit QDR II+ SRAM Four-Word Burst Architecture

No Preview Available !

CY7C15632KV18
Logic Block Diagram – CY7C15632KV18
D[17:0]
18
A(19:0) 20
Address
Register
Write Write Write Write
Reg Reg Reg Reg
Address
Register
20 A(19:0)
K
K
DOFF
VREF
WPS
BWS[1:0]
CLK
Gen.
Control
Logic
Read Data Reg.
72
36
36
Control
Logic
RPS
Reg.
Reg.
Reg. 18
18
18
18
18
CQ
CQ
Q[17:0]
QVLD
Document Number: 001-54932 Rev. *K
Page 2 of 30


Part Number CY7C15632KV18
Description 72-Mbit QDR II+ SRAM Four-Word Burst Architecture
Maker Cypress Semiconductor
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