Description
The CY7C1522V18, CY7C1529V18, CY7C1523V18, CY7C1524V18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II SIO (Double Data Rate Separate I/O) architecture..
Features
- 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36).
- 300-MHz clock for high bandwidth.
- 2-Word burst for reducing address bus frequency.
- Double Data Rate (DDR) interfaces (data transferred at 600 MHz) @ 300 MHz.
- Two input clocks (K and K) for precise DDR timing.
- SRAM uses rising edges only.
- Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches.
- Echo clocks (CQ and CQ) simplify data captu.
