This datasheet includes multiple variants, all published together in a single manufacturer document.
| Part number | CY7C1526JV18 |
|---|---|
| Datasheet | CY7C1526JV18 CY7C1511JV18 Datasheet (PDF) |
| File Size | 719.20 KB |
| Manufacturer | Cypress (now Infineon) |
| Description | 72-Mbit QDR-II SRAM 4-Word Burst Architecture |
|
|
QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations.
See all Cypress (now Infineon) datasheets
| Part Number | Description |
|---|---|
| CY7C1526AV18 | 72-Mbit QDR-II SRAM 4-Word Burst Architecture |
| CY7C1526KV18 | 72-Mbit QDR-II SRAM Four-Word Burst Architecture |
| CY7C1526V18 | (CY7C15xxV18) SRAM 4-Word Burst Architecture |
| CY7C1520KV18 | 72-Mbit DDR-II SRAM Two-Word Burst Architecture |
| CY7C1520V18 | 1.8V Synchronous Pipelined SRAM |
| CY7C1521KV18 | 72-Mbit DDR II SRAM Four-Word Burst Architecture |
| CY7C1521V18 | 1.8V Synchronous Pipelined SRAM |
| CY7C1522AV18 | 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
| CY7C1522JV18 | 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
| CY7C1522KV18 | 72-Mbit DDR II SIO SRAM 2-Word Burst Architecture |
