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CY7C1524AV18 Datasheet

72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture

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CY7C1522AV18, CY7C1529AV18
CY7C1523AV18, CY7C1524AV18
72-Mbit DDR-II SIO SRAM 2-Word
Burst Architecture
Features
Functional Description
72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36)
300 MHz clock for high bandwidth
2-word burst for reducing address bus frequency
Double Data Rate (DDR) interfaces
(data transferred at 600 MHz) at 300 MHz
Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
Synchronous internally self-timed writes
DDR-II operates with 1.5 cycle read latency when the DLL is
enabled
Operates similar to a DDR-I device with 1 cycle read latency in
DLL off mode
1.8V core power supply with HSTL inputs and outputs
Variable drive HSTL output buffers
Expanded HSTL output voltage (1.4V–VDD)
Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)
Offered in both Pb-free and non Pb-free packages
JTAG 1149.1 compatible test access port
Delay Lock Loop (DLL) for accurate data placement
Configurations
The CY7C1522AV18, CY7C1529AV18, CY7C1523AV18, and
CY7C1524AV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with Double Data Rate Separate IO (DDR-II SIO)
architecture. The DDR-II SIO consists of two separate ports: the
read port and the write port to access the memory array. The
read port has data outputs to support read operations and the
write port has data inputs to support write operations. The DDR-II
SIO has separate data inputs and data outputs to completely
eliminate the need to “turn-around” the data bus required with
common IO devices. Access to each port is accomplished
through a common address bus. Addresses for read and write
are latched on alternate rising edges of the input (K) clock. Write
data is registered on the rising edges of both K and K. Read data
is driven on the rising edges of C and C if provided, or on the
rising edge of K and K if C/C are not provided. Each address
location is associated with two 8-bit words in the case of
CY7C1522AV18, two 9-bit words in the case of CY7C1529AV18,
two 18-bit words in the case of CY7C1523AV18, and two 36-bit
words in the case of CY7C1524AV18 that burst sequentially into
or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs are tightly matched to the
two output echo clocks CQ/CQ, eliminating the need to capture
data separately from each individual DDR-II SIO SRAM in the
system design. Output data clocks (C/C) enable maximum
system clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
CY7C1522AV18 – 8M x 8
CY7C1529AV18 – 8M x 9
CY7C1523AV18 – 4M x 18
CY7C1524AV18 – 2M x 36
Selection Guide
Description
Maximum Operating Frequency
Maximum Operating Current
www.DataSheet4U.com
300 MHz
300
x8 900
x9 900
x18 950
x36 1080
278 MHz
278
855
855
880
1000
250 MHz
250
800
800
800
900
200 MHz
200
700
700
700
750
167 MHz
167
650
650
650
650
Unit
MHz
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-06981 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 14, 2007
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Cypress Semiconductor Electronic Components Datasheet

CY7C1524AV18 Datasheet

72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture

No Preview Available !

CY7C1522AV18, CY7C1529AV18
CY7C1523AV18, CY7C1524AV18
Logic Block Diagram (CY7C1522AV18)
D[7:0]
8
A(21:0) 22
Address
Register
K
K
DOFF
CLK
Gen.
R/W
VREF
LD
NWS[1:0]
Control
Logic
Write
Write
Data Reg Data Reg
Read Data Reg.
16
8
8
Control
Logic
LD
R/W
C
C
Reg.
Reg.
Reg. 8
8
8
CQ
CQ
Q[7:0]
Logic Block Diagram (CY7C1529AV18)
D[8:0]
9
A(21:0) 22
Address
Register
K
K
DOFF
CLK
Gen.
R/W
www.DataSheeVt4RUE.Fcom
LD
BWS[0]
Control
Logic
Write
Write
Data Reg Data Reg
Read Data Reg.
18
9
9
Control
Logic
LD
R/W
C
C
Reg.
Reg.
Reg. 9
9
9
CQ
CQ
Q[8:0]
Document #: 001-06981 Rev. *C
Page 2 of 30
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Part Number CY7C1524AV18
Description 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
Maker Cypress Semiconductor
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CY7C1524AV18 Datasheet PDF






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Cypress Semiconductor





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