CY7C1523KV18 72-Mbit DDR II SIO SRAM 2-Word Burst Architecture Datasheet

CY7C1523KV18 Key Features

SRAM uses rising edges only Two Input Clocks for Output Data (C and C) to minimize Clock Skew and Flight Time mismatches
Supports both 1.5 V and 1.8 V IO supply Available in 165-ball FBGA Package (13 × 15 × 1.4 mm) Offered in both Pb-free an

Part Number	Description
CY7C1523AV18	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1523JV18	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1523V18	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1520KV18	72-Mbit DDR-II SRAM Two-Word Burst Architecture
CY7C1520V18	1.8V Synchronous Pipelined SRAM