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CY7C1522V18 - 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture

Description

The CY7C1522V18, CY7C1529V18, CY7C1523V18, CY7C1524V18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II SIO (Double Data Rate Separate I/O) architecture.

The DDR-II SIO consists of two separate ports to access the memory array.

Features

  • 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36).
  • 300-MHz clock for high bandwidth.
  • 2-Word burst for reducing address bus frequency.
  • Double Data Rate (DDR) interfaces (data transferred at 600 MHz) @ 300 MHz.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches.
  • Echo clocks (CQ and CQ) simplify data captu.

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Datasheet Details

Part number CY7C1522V18
Manufacturer Cypress Semiconductor
File Size 491.53 KB
Description 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
Datasheet download datasheet CY7C1522V18 Datasheet
Additional preview pages of the CY7C1522V18 datasheet.

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Full PDF Text Transcription

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CY7C1522V18 CY7C1529V18 CY7C1523V18 CY7C1524V18 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features • 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36) • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency • Double Data Rate (DDR) interfaces (data transferred at 600 MHz) @ 300 MHz • Two input clocks (K and K) for precise DDR timing — SRAM uses rising edges only • Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches • Echo clocks (CQ and CQ) simplify data capture in high-speed systems • Synchronous internally self-timed writes • 1.8V core power supply with HSTL inputs and outputs • Variable drive HSTL output buffers • Expanded HSTL output voltage (1.4V–VDD) • Available in 165-ball FBGA package (15 x 17 x 1.
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