CY7C1515KV18
Features
- Separate independent read and write data ports
- Supports concurrent transactions
- 333 MHz clock for high bandwidth
- Four-word burst for reducing address bus frequency
- Double data rate (DDR) interfaces on both read and write ports
(data transferred at 666 MHz) at 333 MHz
- Two input clocks (K and K) for precise DDR timing
- SRAM uses rising edges only
- Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
- Echo clocks (CQ and CQ) simplify data capture in high speed systems
- Single multiplexed address input bus latches address inputs for read and write ports
- Separate port selects for depth expansion
- Synchronous internally self-timed writes
- QDR® II operates with 1.5 cycle read latency when DOFF is asserted HIGH
- Operates similar to QDR I device with one cycle read latency when DOFF is asserted Low
- Available in × 9, × 18, and × 36 configurations
- Full data coherency, providing most current data
- Core VDD = 1.8 V (±0.1...
