Datasheet Details
| Part number | CY7C1515V18 |
|---|---|
| Manufacturer | Cypress (Infineon) |
| File Size | 561.73 KB |
| Description | (CY7C15xxV18) SRAM 4-Word Burst Architecture |
| Datasheet |
 CY7C1515V18 Datasheet
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Description
The CY7C1511V18, CY7C1526V18, CY7C1513V18, and CY7C1515V18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture.
QDR-II architecture consists of two separate ports to access the memory array.
Features
- Separate Independent Read and Write Data Ports.
- Supports concurrent transactions.
- 250-MHz Clock for High Bandwidth.
- 4-Word Burst for reducing address bus frequency.
- Double Data Rate (DDR) interfaces on both Read and Write Ports (data transferred at 500 MHz) at 250 MHz.
- Two input clocks (K and K) for precise DDR timing.
- SRAM uses rising edges only.
- Two output clocks (C and C) accounts for clock skew and flight time mismatchi.