CY7C1511KV18 architecture equivalent, (cy7c15xxkv18) 72-mbit qdr ii sram 4-word burst architecture.
* Separate independent read and write data ports
* Supports concurrent transactions
* 333 MHz clock for high bandwidth
* Four-word burst for reducing addr.
The CY7C1526KV18, CY7C1513KV18, and CY7C1515KV18 are 1.8-V synchronous pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port .
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