CY7C1511KV18
Description
Maximum operating frequency Maximum operating current 333 MHz 300 MHz 250 MHz 200 MHz Unit 333 300 250 200 MHz × 9 600 560 490 Not Offered mA × 18 620 570 500 440 × 36 850 790 680 Not Offered Cypress Semiconductor Corporation - 198 Champion Court Document Number: 001-00435 Rev.
Key Features
- Separate independent read and write data ports ❐ Supports concurrent transactions
- 333 MHz clock for high bandwidth
- Four-word burst for reducing address bus frequency
- Double data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz
- Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only
- Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
- Echo clocks (CQ and CQ) simplify data capture in high speed systems
- Single multiplexed address input bus latches address inputs for read and write ports
- Separate port selects for depth expansion
- Synchronous internally self-timed writes
