CY7C1511JV18 Key Features
- 8M x 8 CY7C1526JV18
- 8M x 9 CY7C1513JV18
- 4M x 18 CY7C1515JV18
- 2M x 36
- Supports concurrent transactions 300 MHz clock for high bandwidth 4-word burst for reducing address bus frequency Double
| Part Number | Description |
|---|---|
| CY7C1511AV18 | 72-Mbit QDR-II SRAM 4-Word Burst Architecture |
| CY7C1511KV18 | (CY7C15xxKV18) 72-Mbit QDR II SRAM 4-Word Burst Architecture |
| CY7C1511V18 | (CY7C15xxV18) SRAM 4-Word Burst Architecture |
| CY7C1510AV18 | 72-Mbit QDR-II SRAM 2-Word Burst Architecture |
| CY7C1510V18 | 1.8V Synchronous Pipelined SRAM |