CY7C1511JV18 Datasheet 72-Mbit QDR-II SRAM 4-Word Burst Architecture

Manufacturer: Cypress (now Infineon)

Datasheet Details

Part number	CY7C1511JV18
Manufacturer	Cypress (now Infineon)
File Size	719.20 KB
Description	72-Mbit QDR-II SRAM 4-Word Burst Architecture
Download	CY7C1511JV18 Download (PDF)

The CY7C1511JV18, CY7C1526JV18, CY7C1513JV18, and CY7C1515JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture.

QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array.

The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations.

CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 72-Mbit QDR™-II SRAM 4-Word Burst.

Configurations CY7C1511JV18.
8M x 8 CY7C1526JV18.
8M x 9 CY7C1513JV18.
4M x 18 CY7C1515JV18.
2M x 36 Separate independent read and write data ports.
Supports concurrent transactions 300 MHz clock for high bandwidth 4-word burst for reducing address bus frequency Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 600 MHz) at 300 MHz Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.

Part Number	Description
CY7C1511AV18	72-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1511KV18	(CY7C15xxKV18) 72-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C1511V18	(CY7C15xxV18) SRAM 4-Word Burst Architecture
CY7C1510AV18	72-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1510V18	1.8V Synchronous Pipelined SRAM
CY7C1512	64K x 8 Static RAM
CY7C1512AV18	72-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1512KV18	72-Mbit QDR II SRAM Two-Word Burst Architecture
CY7C1512V18	1.8V Synchronous Pipelined SRAM
CY7C1513AV18	72-Mbit QDR-II SRAM 4-Word Burst Architecture