| Part number | CY7C1511JV18 |
|---|---|
| Datasheet | CY7C1511JV18_CypressSemiconductor.pdf |
| File Size | 719.20 KB |
| Manufacturer | Cypress (now Infineon) |
| Description | 72-Mbit QDR-II SRAM 4-Word Burst Architecture |
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QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations.
See all Cypress (now Infineon) datasheets
| Part Number | Description |
|---|---|
| CY7C1511AV18 | 72-Mbit QDR-II SRAM 4-Word Burst Architecture |
| CY7C1511KV18 | (CY7C15xxKV18) 72-Mbit QDR II SRAM 4-Word Burst Architecture |
| CY7C1511V18 | (CY7C15xxV18) SRAM 4-Word Burst Architecture |
| CY7C1510AV18 | 72-Mbit QDR-II SRAM 2-Word Burst Architecture |
| CY7C1510V18 | 1.8V Synchronous Pipelined SRAM |
| CY7C1512 | 64K x 8 Static RAM |
| CY7C1512AV18 | 72-Mbit QDR-II SRAM 2-Word Burst Architecture |
| CY7C1512KV18 | 72-Mbit QDR II SRAM Two-Word Burst Architecture |
| CY7C1512V18 | 1.8V Synchronous Pipelined SRAM |
| CY7C1513AV18 | 72-Mbit QDR-II SRAM 4-Word Burst Architecture |
