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Cypress Semiconductor Electronic Components Datasheet

CY7C1379C Datasheet

9-Mbit (256K x 32) Flow-through SRAM

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CY7C1379C
9-Mbit (256K x 32) Flow-through SRAM
with NoBL™ Architecture
Features
Functional Description[1]
• Can support up to 133-MHz bus operations with zero
wait states
— Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™
devices
• Internally self-timed output buffer control to eliminate
the need to use OE
• Registered inputs for flow-through operation
• Byte Write capability
• 256K x 32 common I/O architecture
• Single 3.3V power supply (VDD)
• Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Asynchronous Output Enable
• Available in JEDEC-standard lead-free 100-Pin TQFP,
lead-free and non lead-free 165-Ball FBGA package
• Burst Capability—linear or interleaved burst order
• Low standby power
Logic Block Diagram–CY7C1379C (256K x 36)
The CY7C1379C is a 3.3V, 256K x 32 Synchronous
Flow-through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
insertion of wait states. The CY7C1379C is equipped with the
advanced No Bus Latency™ (NoBL™) logic required to
enable consecutive Read/Write operations with data being
transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent Write-Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
Write operations are controlled by the two Byte Write Select
(BW[A:D]) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
A0, A1, A
MODE
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CEN
CE
ADV/LD
BWA
BWB
BWC
BWD
WE
OE
CE1
CE2
CE3
ZZ
ADDRESS
REGISTER
A1
A0
D1
D0
ADV/LD
C
WRITE ADDRESS
REGISTER
Q1
Q0
A1'
A0'
BURST
LOGIC
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
READ LOGIC
SLEEP
Control
INPUT E
REGISTER
O
U
T
DP
AU
TT
A
B
SU
TF
EF
EE
RR
IS
NE
G
DQs
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05688 Rev. *D
Revised September 14, 2006


Cypress Semiconductor Electronic Components Datasheet

CY7C1379C Datasheet

9-Mbit (256K x 32) Flow-through SRAM

No Preview Available !

Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Pin Configurations
133 MHz
6.5
250
40
100-Pin TQFP Pinout
CY7C1379C
100 MHz
7.5
180
40
Unit
ns
mA
mA
NC
BYTE C
DQC
DQC
VDDQ
VSS
DQC
DQC
DQC
DQC
VSS
VDDQ
DQC
DQC
VSS/DNU
VDD
NC
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BYTE D
VSS
DQD
DQD
VDDQ
VSS
DQD
DQD
DQD
DQD
VSS
VDDQ
DQD
DQD
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1379C
80 NC
79 DQB
78 DQB
77 VDDQ
76 VSS
75 DQB
74
DQB
BYTE B
73 DQB
72 DQB
71 VSS
70 VDDQ
69 DQB
68 DQB
67 VSS
66 NC
65 VDD
64 ZZ
63 DQA
62 DQA
61 VDDQ
60 VSS
59 DQA
58 DQA BYTE A
57 DQA
56 DQA
55 VSS
54 VDDQ
53 DQA
52 DQA
51 NC
Document #: 38-05688 Rev. *D
Page 2 of 15


Part Number CY7C1379C
Description 9-Mbit (256K x 32) Flow-through SRAM
Maker Cypress Semiconductor
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CY7C1379C Datasheet PDF






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