Datasheet4U Logo Datasheet4U.com

CY7C1373DV25 - (CY7C1371DV25 / CY7C1373DV25) Flow-Through SRAM

Description

The CY7C1371DV25/CY7C1373DV25 is a 2.5V, 512K x 36/1M x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states.

Features

  • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles.
  • Can support up to 133-MHz bus operations with zero wait states.
  • Data is transferred on every clock.
  • Pin compatible and functionally equivalent to ZBT™ devices.
  • Internally self-timed output buffer control to eliminate the need to use OE.
  • Registered inputs for flow-through operation.
  • Byte Write capability.
  • 2.5V core power supply (VDD).

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
CY7C1373C 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture Cypress
CY7C1370C 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture Cypress
CY7C1370CV25 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture Cypress
CY7C1370D 18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM Cypress
CY7C1371C 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture Cypress

Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C1373D 18-Mbit (512 K x 36/1 M x 18) Flow-Through SRAM
CY7C1373B (CY7C1371B / CY7C1373B) 512K x 36/1M x 18 Flow-Thru SRAM
CY7C1373KV33 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1370B (CY7C1370B / CY7C1372B) 512K X 36/1M X 18 Pipelined SRAM
CY7C1370DV25 18-Mbit (512K x 36/1M x 18) Pipelined SRAM

Full PDF Text Transcription

Click to expand full text
CY7C1371DV25 www.DataSheet4U.com CY7C1373DV25 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL™ Architecture Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through operation • Byte Write capability • 2.5V core power supply (VDD) • 2.5V I/O power supply (VDDQ) • Fast clock-to-output times — 6.
Published: |