CY7C1373B Datasheet | Cypress

Features - Pin patible and functionally equivalent to ZBT devices - Supports 117-MHz bus operations with zero wait states - Data is transferred on every clock - Internally self-timed output buffer control to eliminate the need to use asynchronous OE - Registered inputs for flow-thru operation - Byte Write capability - mon I/O architecture - Fast clock-to-output times - 7.5 ns (for 117-MHz device) - 8.5 ns (for 100-MHz device) - - - - - - - - - 10.0ns (for 83-MHz device) Single 3.3V - 5% and +10% power supply VDD Separate VDDQ for 3.3V or 2.5V I/O Clock enable (CEN) pin to suspend operation Synchronous self-timed writes Available in 100 TQFP and 119 BGA packages Burst capability - linear or interleaved burst order JTAG boundary scan for BGA packaging version Automatic power down available using ZZ mode or CE deselect Functional Description The CY7C1371B/CY7C1373B is 3.3V, 512K × 36 and 1M × 18 synchronous flow-thru burst SRAMs, respectively designed to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1371B/ CY7C1373B is equipped with the advanced No Bus Latency™ (No BL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write/Read transitions.The CY7C1371B/CY7C1373B is pin patible and functionally equivalent to ZBT devices. All synchronous inputs pass through input registers controlled by the rising edge of the clock.The clock input is qualified by the Clock enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 7.5 ns (117-MHz device). Write operations are controlled by the byte Write Selects (BWSa,b,c,d for CY7C1371B and BWSa,b for CY7C1373B) and a Write enable (WE) input. All writes are conducted with on-chip synchronous self-timed Write...