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Cypress Semiconductor Electronic Components Datasheet

CY7C1373B Datasheet

(CY7C1371B / CY7C1373B) 512K x 36/1M x 18 Flow-Thru SRAM

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73B CY7C1371B
CY7C1373B
512K x 36/1M x 18 Flow-Thru SRAM with NoBLArchitecture
Features
Pin compatible and functionally equivalent to ZBT
devices
• Supports 117-MHz bus operations with zero wait states
— Data is transferred on every clock
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Registered inputs for flow-thru operation
• Byte Write capability
• Common I/O architecture
• Fast clock-to-output times
— 7.5 ns (for 117-MHz device)
— 8.5 ns (for 100-MHz device)
— 10.0ns (for 83-MHz device)
• Single 3.3V –5% and +10% power supply VDD
• Separate VDDQ for 3.3V or 2.5V I/O
• Clock enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Available in 100 TQFP and 119 BGA packages
• Burst capability – linear or interleaved burst order
• JTAG boundary scan for BGA packaging version
• Automatic power down available using ZZ mode or CE
deselect
Functional Description
The CY7C1371B/CY7C1373B is 3.3V, 512K × 36 and 1M × 18
synchronous flow-thru burst SRAMs, respectively designed to
support unlimited true back-to-back Read/Write operations
without the insertion of wait states. The CY7C1371B/
CY7C1373B is equipped with the advanced No Bus Latency
(NoBL) logic required to enable consecutive Read/Write
operations with data being transferred on every clock cycle.
This feature dramatically improves the throughput of data
through the SRAM, especially in systems that require frequent
Write/Read transitions.The CY7C1371B/CY7C1373B is pin
compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock.The clock input is qualified by
the Clock enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 7.5 ns (117-MHz
device).
Write operations are controlled by the byte Write Selects
(BWSa,b,c,d for CY7C1371B and BWSa,b for CY7C1373B) and
a Write enable (WE) input. All writes are conducted with
on-chip synchronous self-timed Write circuitry. ZZ may be tied
to LOW if it is not used.
Synchronous Chip enables (CE1, CE2, CE3 on the TQFP, CE1
on the BGA) and an asynchronous Output enable (OE)
provide for easy bank selection and output three-state control.
In order to avoid bus contention, the output drivers are
synchronously three-stated during the data portion of a Write
sequence.
www.DaLtaoSgheicet4BUl.ococmk Diagram
CLK
ADV/LD
CY7C1371 CY7C1373
AX X = 18:0 X = 19:0
DQX X= a, b, c, d X = a, b
DPX X = a, b, c, d X = a, b
BWSX X = a, b, c, d X = a, b
Ax
CEN
CE1
CE2
CE3
WE
BWSx
Mode
OE
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Control
and Write
Logic
117 MHz
7.5
250
20
D
CE
Data-In
Q
REG.
256K X 36/
512K X 18
Memory
Array
100 MHz
8.5
225
20
83 MHz
10.0
185
20
DQx
DPx
Unit
ns
mA
mA
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05198 Rev. **
Revised February 4, 2002


Cypress Semiconductor Electronic Components Datasheet

CY7C1373B Datasheet

(CY7C1371B / CY7C1373B) 512K x 36/1M x 18 Flow-Thru SRAM

No Preview Available !

Pin Configurations
100-pin TQFP Packages
CY7C1371B
CY7C1373B
DPc 1
DQc 2
DQc
VDDQ
3
4
VSS
DQc
5
6
DQc 7
DQc 8
DQc
VSS
VDDQ
9
10
11
DQc 12
DQc
NC
VDD
NC
VSS
DQd
13
14
15
16
17
18
DQd 19
VDDQ 20
VSS 21
DQd 22
DQd 23
DQd 24
DQd 25
www.DataVSSSheet42U6.com
VDDQ 27
DQd 28
DQd 29
DPd 30
CY7C1371B
(512K × 36)
80 DPb NC 1
79 DQb NC 2
78 DQb NC 3
77 VDDQ VDDQ 4
76 VSS
VSS 5
75 DQb NC 6
74 DQb NC 7
73 DQb DQb 8
72 DQb DQb 9
71 VSS
VSS
10
70 VDDQ VDDQ 11
69 DQb DQb 12
68 DQb DQb 13
67 VSS
NC 14
66 NC
VDD
15
65 VDD NC
16
64 ZZ
VSS
17
63 DQa DQb 18
62 DQa DQb 19
61 VDDQ VDDQ 20
60 VSS
VSS
21
59 DQa DQb 22
58 DQa DQb 23
57 DQa DPb 24
56 DQa NC 25
55 VSS
VSS 26
54 VDDQ VDDQ 27
53 DQa NC 28
52 DQa NC 29
51 DPa NC 30
CY7C1373B
(1M × 18)
80 A
79 NC
78 NC
77 VDDQ
76 VSS
75 NC
74 DPa
73 DQa
72 DQa
71 VSS
70 VDDQ
69 DQa
68 DQa
67 VSS
66 NC
65 VDD
64 ZZ
63 DQa
62 DQa
61 VDDQ
60 VSS
59 DQa
58 DQa
57 NC
56 NC
55 VSS
54 VDDQ
53 NC
52 NC
51 NC
Document #: 38-05198 Rev. **
Page 2 of 26


Part Number CY7C1373B
Description (CY7C1371B / CY7C1373B) 512K x 36/1M x 18 Flow-Thru SRAM
Maker Cypress Semiconductor
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CY7C1373B Datasheet PDF






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