Description
The CY7C1355C/CY7C1357C is a 3.3V, 256K x 36/ 512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states.
Features
- No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles.
- Can support up to 133-MHz bus operations with zero wait states.
- Data is transferred on every clock.
- Pin compatible and functionally equivalent to ZBT™ devices.
- Internally self-timed output buffer control to eliminate the need to use OE.
- Registered inputs for flow-through operation.
- Byte Write capability.
- 3.3V/2.5V I/O power supply.
CY7C1355C Datasheet
