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CY7C1355C - (CY7C1355C / CY7C1357C) 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM

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General Description

[1] The CY7C1355C/CY7C1357C is a 3.3V, 256K x 36/ 512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states.

The CY7C1355C/CY7C1357C is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle.

This

Overview

www.DataSheet4U.com PRELIMINARY CY7C1355C CY7C1357C 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL™.

Key Features

  • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles.
  • Can support up to 133-MHz bus operations with zero wait states.
  • Data is transferred on every clock.
  • Pin compatible and functionally equivalent to ZBT™ devices.
  • Internally self-timed output buffer control to eliminate the need to use OE.
  • Registered inputs for flow-through operation.
  • Byte Write capability.
  • 3.3V/2.5V I/O power supply.

More Datasheets from Cypress (now Infineon)

Part Number Description
CY7C1355A (CY7C1355A / CY7C1357A) 256K x 36/512K x 18 Synchronous Flow-Thru SRAM
CY7C1355B (CY7C1355B / CY7C1357B) 9-Mb (256K x 36/512K x 18) Flow-Through SRAM
CY7C135 4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM
CY7C1350G 4-Mbit (128K x 36) Pipelined SRAM
CY7C1351 128Kx36 Flow-Through SRAM
CY7C1351F 4-Mb (128K x 36) Flow-through SRAM
CY7C1351G 4-Mbit (128K x 36) Flow-Through SRAM
CY7C1352 256K x18 Pipelined SRAM
CY7C1352F 4-Mbit (256K x 18) Pipelined SRAM
CY7C1352G 4-Mbit (256K x 18) Pipelined SRAM