Datasheet4U Logo Datasheet4U.com

CY7C1355B Datasheet (CY7C1355B / CY7C1357B) 9-Mb (256K x 36/512K x 18) Flow-Through SRAM

Manufacturer: Cypress (now Infineon)

General Description

[1] The CY7C1355B/CY7C1357B is a 3.3V, 256K x 36/ 512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states.

The CY7C1355B/CY7C1357B is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle.

This

Overview

www.DataSheet4U.com CY7C1355B CY7C1357B 9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL™.

Key Features

  • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles.
  • Can support up to 133-MHz bus operations with zero wait states.
  • Data is transferred on every clock.
  • Pin compatible and functionally equivalent to ZBT™ devices.
  • Internally self-timed output buffer control to eliminate the need to use OE.
  • Registered inputs for flow-through operation.
  • Byte Write capability.
  • 3.3V/2.5V I/O power supply.