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Cypress Semiconductor Electronic Components Datasheet

CY7C1347G Datasheet

4-Mbit (128K x 36) Pipelined Sync SRAM

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PRELIMINARY
CY7C1347G
4-Mbit (128K x 36) Pipelined Sync SRAM
Features
• Fully registered inputs and outputs for pipelined
operation
• 128K by 36 common I/O architecture
• 3.3V core power supply
• 2.5V/3.3V I/O operation
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
— 2.6 ns (for 225-MHz device)
— 2.8 ns (for 200-MHz device)
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device)
— 4.5 ns (for 100-MHz device)
• User-selectable burst counter supporting Intel®
Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Lead-Free 100-pin TQFP, 119-pin BGA and 165-pin
fBGA packages
• “ZZ” Sleep Mode option and Stop Clock option
• Available in Industrial and Commercial temperature
ranges
Functional Description[1]
The CY7C1347G is a 3.3V, 128K by 36 synchronous-pipelined
SRAM designed to support zero-wait-state secondary cache
with minimal glue logic.
CY7C1347G I/O pins can operate at either the 2.5V or the
3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise is 2.6 ns (250-MHz
device).
CY7C1347G supports either the interleaved burst sequence
used by the Intel Pentium processor or a linear burst sequence
used by processors such as the PowerPC®. The burst
sequence is selected through the MODE pin. Accesses can be
initiated by asserting either the Address Strobe from
Processor (ADSP) or the Address Strobe from Controller
(ADSC) at clock rise. Address advancement through the burst
sequence is controlled by the ADV input. A 2-bit on-chip
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the
rest of the burst access.
Byte write operations are qualified with the four Byte Write
Select (BW[A:D]) inputs. A Global Write Enable (GW) overrides
all byte write inputs and writes data to all four bytes. All writes
are conducted with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to provide proper
data during depth expansion, OE is masked during the first
clock of a read cycle when emerging from a deselected state.
Logic Block Diagram
A0, A1, A
MODE
ADV
CLK
ADDRESS
REGISTER
ADSC
ADSP
BWD
BWC
BWB
BWA
BWE
GW
CE1
CE2
CE3
OE
DQD ,DQPD
BYTE
WRITE REGISTER
DQC ,DQPC
BYTE
WRITE REGISTER
DQB ,DQPB
BYTE
WRITE REGISTER
DQA ,DQPA
BYTE
WRITE REGISTER
ENABLE
REGISTER
2 A[1:0]
Q1
BURST
COUNTER
CLR AND Q0
LOGIC
PIPELINED
ENABLE
DQD ,DQPD
BYTE
WRITE DRIVER
DQC ,DQPC
BYTE
WRITE DRIVER
DQB ,DQPB
BYTE
WRITE DRIVER
DQA ,DQPA
BYTE
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
DQPA
DQPB
DQPC
DQPD
INPUT
REGISTERS
ZZ SLEEP
CONTROL
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05516 Rev. *A
Revised October 14, 2004
DataSheet4 U .com


Cypress Semiconductor Electronic Components Datasheet

CY7C1347G Datasheet

4-Mbit (128K x 36) Pipelined Sync SRAM

No Preview Available !

www.DataSheet4U.com
PRELIMINARY
CY7C1347G
Selection Guide
-250
-225
-200
-166
-133
Maximum Access Time
2.6 2.6 2.8 3.5 4.0
Maximum Operating Current
325 290 265 240 225
Maximum CMOS Standby Current
40 40 40 40 40
Shaded areas contain advance information. Please contact your local Cypress Sales representative for availability of these parts.
Pin Configurations
100-Pin TQFP
-100
4.5
205
40
Unit
ns
mA
mA
BYTE C
BYTE D
DQPC
DQC
DQC
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1347G
80 DQPB
79 DQB
78 DQB
77 VDDQ
76 VSSQ
75 DQB
74
DQB
BYTE B
73 DQB
72 DQB
71 VSSQ
70 VDDQ
69 DQB
68 DQB
67 VSS
66 NC
65 VDD
64 ZZ
63 DQA
62 DQA
61 VDDQ
60 VSSQ
59 DQA
58 DQA
57
DQA
BYTE A
56 DQA
55 VSSQ
54 VDDQ
53 DQA
52 DQA
51 DQPA
Document #: 38-05516 Rev. *A
DataSheet4 U .com
Page 2 of 19


Part Number CY7C1347G
Description 4-Mbit (128K x 36) Pipelined Sync SRAM
Maker Cypress Semiconductor
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CY7C1347G Datasheet PDF






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