CY7C1347G Overview
[1] The CY7C1347G is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous inputs pass through input registers controlled by the rising edge of the clock.
CY7C1347G Key Features
- Fully registered inputs and outputs for pipelined operation
- 128K by 36 mon I/O architecture
- 3.3V core power supply
- 2.5V/3.3V I/O operation
- Fast clock-to-output times
- 2.6 ns (for 250-MHz device)
- 2.6 ns (for 225-MHz device)
- 2.8 ns (for 200-MHz device)
- 3.5 ns (for 166-MHz device)
- 4.0 ns (for 133-MHz device)