CY7C1316KV18 - 18-Mbit DDR II SRAM Two-Word Burst Architecture

Cypress Semiconductor

The CY7C1316KV18 by Cypress Semiconductor is a 18-Mbit DDR II SRAM Two-Word Burst Architecture. Below is the official datasheet preview.

Datasheet Details

Part number	CY7C1316KV18
Manufacturer	Cypress Semiconductor
File Size	1.45 MB
Description	18-Mbit DDR II SRAM Two-Word Burst Architecture
Datasheet	CY7C1316KV18_CypressSemiconductor.pdf
Additional preview pages of the CY7C1316KV18 datasheet.

The CY7C1316KV18, CY7C1916KV18, CY7C1318KV18, and CY7C1320KV18 are 1.8 V synchronous pipelined SRAM equipped with DDR II architecture.

Configurations CY7C1316KV18.
2 M × 8 CY7C1916KV18.
2 M × 9 CY7C1318KV18.
1 M × 18 CY7C1320KV18.
512 K × 36 18-Mbit density (2 M × 8, 2 M × 9, 1 M × 18, 512 K × 36) 333-MHz clock for high bandwidth Two-word burst for reducing address bus frequency Double data rate (DDR) interfaces  (data transferred at 666 MHz) at 333 MHz Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only Two input clocks for out.

📁 CY7C1316KV18 Similar Datasheet

CY7C131AE - 1K/2K x 8 Dual-Port Static RAM (Cypress)
CY7C131E - 1K/2K x 8 Dual-Port Static RAM (Cypress)
CY7C136AE - 1K/2K x 8 Dual-Port Static RAM (Cypress)
CY7C136E - 1K/2K x 8 Dual-Port Static RAM (Cypress)
CY7C1370C - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
CY7C1370CV25 - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
CY7C1370D - 18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM (Cypress)
CY7C1371C - 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture (Cypress)

Other Datasheets by Cypress Semiconductor

Published: Apr 15, 2011 |