CY7C1313BV18 (CY7C1x1xBV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture Datasheet

CY7C1313BV18 Key Features

Separate Independent Read and Write data ports
Supports concurrent transactions
300-MHz clock for high bandwidth
4-Word Burst for reducing address bus frequency
Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 600 MHz) at 300 MHz
Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches
Echo clocks (CQ and CQ) simplify data capture in high-speed systems
Single multiplexed address input bus latches address inputs for both Read and Write ports

Part Number	Description
CY7C1313AV18	(CY7C131xAV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
CY7C1313CV18	(CY7C1x1xCV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
CY7C1313JV18	(CY7C1x1xJV18) 18-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C1313KV18	18-Mbit QDR II SRAM Four-Word Burst Architecture
CY7C131	1K x 8 Dual-Port Static RAM