CY7C1313BV18 architecture equivalent, (cy7c1x1xbv18) 18-mb qdrtm-ii sram 4-word burst architecture.
* Separate Independent Read and Write data ports — Supports concurrent transactions
* 300-MHz clock for high bandwidth
* 4-Word Burst for reducing address bus.
The CY7C1311BV18, CY7C1911BV18, CY7C1313BV18, and CY7C1315BV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data O.
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