CY7C1313AV18
Features
- Separate Independent Read and Write Data Ports
- Supports concurrent transactions
- 250-MHz Clock for High Bandwidth
- 4-Word Burst for reducing address bus frequency
- Double Data Rate (DDR) interfaces on both Read and Write Ports (data transferred at 500 MHz) at 250 MHz
- Two input clocks (K and K) for precise DDR timing
- SRAM uses rising edges only
- Two output clocks (C and C) accounts for clock skew and flight time mismatching
- Echo clocks (CQ and CQ) simplify data capture in high speed systems
- Single multiplexed address input bus latches address inputs for both Read and Write ports
- Separate Port Selects for depth expansion
- Synchronous internally self-timed writes
- Available in ×8, ×18, and ×36 configurations
- Full data coherancy providing most current data
- Core Vdd=1.8(+/-0.1V);I/O Vddq=1.4V to Vdd)
- 13 × 15 x 1.4 mm 1.0-mm pitch FBGA package, 165-ball (11 × 15 matrix)
- Variable drive HSTL output buffers
- JTAG 1149.1 patible test access port
- Delay...
