Datasheet Details
- Part number
- CY7C1303BV18
- Manufacturer
- Cypress Semiconductor
- File Size
- 677.60 KB
- Datasheet
- CY7C1303BV18-CypressSemiconductor.pdf
- Description
- 18-Mbit Burst of 2 Pipelined SRAM
Separate independent Read and Write data ports. Supports concurrent transactions. 167-MHz Clock for high bandwidth. 2.5 ns Clock-to-Valid access time. 2-Word Burst on all accesses. Double Data Rate (DDR) interfaces on both Read and Write Ports (data transferred at 333 MHz) @167 MHz. Two input clocks (K and K) for precise DDR timing. SRAM uses rising edges only. Two input clocks for output data (C and C) to minimiz.
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