CY7C1302CV25 Datasheet | Cypress

Features - Separate independent Read and Write data ports - Supports concurrent transactions - 167-MHz clock for high bandwidth - 2.5 ns clock-to-Valid access time - 2-word burst on all accesses - Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 333 MHz) @ 167 MHz - Two input clocks (K and K) for precise DDR timing - SRAM uses rising edges only - Two output clocks (C and C) account for clock skew and flight time mismatching - Single multiplexed address input bus latches address inputs for both Read and Write ports - Separate Port Selects for depth expansion - Synchronous internally self-timed writes - 2.5V core power supply with HSTL Inputs and Outputs - 13 x 15 x 1.4 mm 1.0-mm pitch f BGA package, 165 ball (11 x 15 matrix) - Variable drive HSTL output buffers - Expanded HSTL output voltage (1.4V- 1.9V) - JTAG Interface Functional Description The CY7C1302CV25 is a 2.5V Synchronous Pipelined SRAM equipped with QDR™ architecture. QDR architecture consists of two separate ports to access the memory array. The Read port has dedicated data outputs to support Read operations and the Write Port has dedicated data inputs to support Write operations. Access to each port is acplished through a mon address bus. The Read address is latched on the rising edge of the K clock and the Write address is latched on the rising edge of K clock. QDR has separate data inputs and data outputs to pletely eliminate the need to “turn-around” the data bus required with mon I/O devices. Accesses to the CY7C1302CV25 Read and Write ports are pletely independent of one another. All accesses are initiated synchronously on the rising edge of the positive input clock (K). In order to maximize data throughput, both Read and Write ports are equipped with DDR interfaces. Therefore, data can be transferred into the device on every rising edge of both input clocks (K and K) and out of the device on every rising edge of the output clock (C and C, or K and K in a single...