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CY7C1302CV25 Datasheet

9-Mbit Burst of Two Pipelined SRAMs

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PREMILINARY
CY7C1302CV25
9-Mbit Burst of Two Pipelined SRAMs
with QDR™ Architecture
Features
• Separate independent Read and Write data ports
— Supports concurrent transactions
• 167-MHz clock for high bandwidth
— 2.5 ns clock-to-Valid access time
• 2-word burst on all accesses
• Double Data Rate (DDR) interfaces on both Read and
Write ports (data transferred at 333 MHz) @ 167 MHz
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
• Two output clocks (C and C) account for clock skew
and flight time mismatching
• Single multiplexed address input bus latches address
inputs for both Read and Write ports
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• 2.5V core power supply with HSTL Inputs and Outputs
• 13 x 15 x 1.4 mm 1.0-mm pitch fBGA package, 165 ball
(11 x 15 matrix)
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V–1.9V)
• JTAG Interface
Configurations
CY7C1302CV25 – 512K x 18
Functional Description
The CY7C1302CV25 is a 2.5V Synchronous Pipelined SRAM
equipped with QDR™ architecture. QDR architecture consists
of two separate ports to access the memory array. The Read
port has dedicated data outputs to support Read operations
and the Write Port has dedicated data inputs to support Write
operations. Access to each port is accomplished through a
common address bus. The Read address is latched on the
rising edge of the K clock and the Write address is latched on
the rising edge of K clock. QDR has separate data inputs and
data outputs to completely eliminate the need to “turn-around”
the data bus required with common I/O devices. Accesses to
the CY7C1302CV25 Read and Write ports are completely
independent of one another. All accesses are initiated
synchronously on the rising edge of the positive input clock
(K). In order to maximize data throughput, both Read and
Write ports are equipped with DDR interfaces. Therefore, data
can be transferred into the device on every rising edge of both
input clocks (K and K) and out of the device on every rising
edge of the output clock (C and C, or K and K in a single clock
domain) thereby maximizing performance while simplifying
system design. Each address location is associated with two
18-bit words that burst sequentially into or out of the device.
Depth expansion is accomplished with a Port Select input for
each port. Each Port Select allows each port to operate
independently.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Logic Block Diagram (CY7C1302CV25)
D[17:0]
A(17:0)
18
K
K
18
Address
Register
CLK
Gen.
Write
Data Reg
Write
Data Reg
256Kx18 256Kx18
Memory Memory
Array
Array
Read Data Reg.
Address
Register
18 A(17:0)
Control
Logic
RPS
C
C
Vref
WPS
BWS0
BWS1
Control
Logic
36 18
18
Reg.
Reg.
Reg. 18
18
18
Q[17:0]
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05491 Rev. *A
Revised June 1, 2004


Cypress Semiconductor Electronic Components Datasheet

CY7C1302CV25 Datasheet

9-Mbit Burst of Two Pipelined SRAMs

No Preview Available !

PREMILINARY
CY7C1302CV25
Selection Guide
Maximum Operating Frequency
Maximum Operating Current
CY7C1302CV25
-167
167
750
CY7C1302CV25
-133
133
650
CY7C1302CV25
-100
100
550
Unit
MHz
mA
Pin Configuration–CY7C1302CV25 (Top View)
1 2 3 4 5 6 7 8 9 10 11
A
NC Gnd/144M NC/36M WPS BWS1
K
NC RPS NC/18M Gnd/72M NC
B NC Q9 D9 A NC K BWS0 A NC NC Q8
C NC
NC
D10 VSS
A
A
A
VSS
NC
Q7
D8
D NC
D11
Q10 VSS VSS VSS VSS VSS
NC
NC
D7
E NC
NC
Q11 VDDQ VSS
VSS
VSS VDDQ
NC
D6
Q6
F
NC
Q12
D12 VDDQ VDD
VSS
VDD VDDQ
NC
NC
Q5
G NC
D13
Q13 VDDQ VDD
VSS
VDD VDDQ
NC
NC
D5
H
NC
VREF VDDQ VDDQ VDD
VSS
VDD VDDQ VDDQ VREF
ZQ
J NC
NC
D14 VDDQ VDD
VSS
VDD VDDQ
NC
Q4
D4
K NC
NC
Q14 VDDQ VDD
VSS
VDD VDDQ
NC
D3
Q3
L
NC
Q15
D15 VDDQ VSS
VSS
VSS VDDQ
NC
NC
Q2
M NC
NC
D16 VSS VSS VSS VSS VSS
NC
Q1
D2
N NC
D17 Q16 VSS
A
A
A
VSS
NC
NC
D1
P NC
NC Q17
A
A
C
A
A NC D0 Q0
R TDO TCK
A
A
A
C
A
A
A
TMS
TDI
Pin Definitions
Name
D[17:0]
WPS
BWS0, BWS1
A
Q[17:0]
RPS
C
I/O
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Outputs-
Synchronous
Input-
Synchronous
Input-
Clock
Description
Data input signals, sampled on the rising edge of K and K clocks during valid Write
operations.
Write Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted
active, a Write operation is initiated. Deasserting will deselect the Write port. Deselecting the
Write port will cause D[17:0] to be ignored.
Byte Write Select 0, 1, active LOW. Sampled on the rising edge of the K and K clocks during
Write operations. Used to select which byte is written into the device during the current portion
of the Write operations. Bytes not written remain unaltered.
BWS0 controls D[8:0] and BWS1 controls D[17:9].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write
Select will cause the corresponding byte of data to be ignored and not written into the device.
Address Inputs. Sampled on the rising edge of the K (read address) and K (write address)
clocks for active Read and Write operations. These address inputs are multiplexed for both Read
and Write operations. Internally, the device is organized as 512K x 18 (2 arrays each of 256K x
18). These inputs are ignored when the appropriate port is deselected.
Data Output signals. These pins drive out the requested data during a Read operation. Valid
data is driven out on the rising edge of both the C and C clocks during Read operations or K and
K when in single clock mode. When the Read port is deselected, Q[17:0] are automatically
three-stated.
Read Port Select, active LOW. Sampled on the rising edge of positive input clock (K). When
active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When
deselected, the pending access is allowed to complete and the output drivers are automatically
three-stated following the next rising edge of the C clock. Each read access consists of a burst
of two sequential transfers.
Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from
the device. C and C can be used together to deskew the flight times of various devices on the
board back to the controller. See application example for further details.
Document #: 38-05491 Rev. *A
Page 2 of 18


Part Number CY7C1302CV25
Description 9-Mbit Burst of Two Pipelined SRAMs
Maker Cypress Semiconductor
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