CY7C1292DV18
Features
- Separate Independent Read and Write data ports
- Supports concurrent transactions
- 250-MHz clock for high bandwidth
- 2-Word Burst on all accesses
- Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 500 MHz) @ 250 MHz
- Two input clocks (K and K) for precise DDR timing
- SRAM uses rising edges only
- Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches
- Echo clocks (CQ and CQ) simplify data capture in high-speed systems
- Single multiplexed address input bus latches address inputs for both Read and Write ports
- Separate Port Selects for depth expansion
- Synchronous internally self-timed writes
- Available in x 18 and x 36 configurations
- Full data coherency, providing most current data
- Core VDD = 1.8V (±0.1V); I/O VDDQ = 1.4V to VDD
- Available in 165-ball FBGA package (13 x 15 x 1.4 mm)
- Offered in both lead-free and non-lead free packages
- Variable drive HSTL output buffers
- JTAG 1149.1...
