CY7C1263XV18 Description
CY7C1263XV18 CY7C1265XV18 36-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) 36-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency).
CY7C1263XV18 Key Features
- Separate Independent Read and Write Data Ports
- Supports concurrent transactions
- 633 MHz Clock for High Bandwidth
- Four-word Burst for Reducing Address Bus Frequency
- Double Data Rate (DDR) Interfaces on both Read and Write
- Available in 2.5 Clock Cycle Latency
- Two Input Clocks (K and K) for precise DDR Timing
- SRAM uses rising edges only
- Echo Clocks (CQ and CQ) simplify Data Capture in High Speed
- Data Valid Pin (QVLD) to indicate Valid Data on the Output