CY7C1241V18 architecture equivalent, 36-mbit qdr-ii sram 4-word burst architecture.
* Separate independent read and write data ports — Supports concurrent transactions
* 300 MHz to 375 MHz clock for high bandwidth
* 4-Word Burst for reducing .
The CY7C1241V18, CY7C1256V18, CY7C1243V18, and CY7C1245V18 are 1.8V Synchronous Pipelined SRAMs, equipped with Quad Data Rate-II+ (QDR-II+) architecture. QDR-II+ architecture consists of two separate ports to access the memory array. The read port ha.
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