CY7C1241V18 Datasheet 36-Mbit QDR-II SRAM 4-Word Burst Architecture

Manufacturer: Cypress (now Infineon)

CY7C1241V18 36-mbit qdr-ii sram 4-word burst architecture by Cypress (now Infineon) - Datasheet Preview

Datasheet Details

Part number	CY7C1241V18
Manufacturer	Cypress (now Infineon)
File Size	Direct Link
Description	36-Mbit QDR-II SRAM 4-Word Burst Architecture
Datasheet	CY7C1241V18 Datasheet

General Description

The CY7C1241V18, CY7C1256V18, CY7C1243V18, and CY7C1245V18 are 1.8V Synchronous Pipelined SRAMs, equipped with Quad Data Rate-II+ (QDR-II+) architecture.

QDR-II+ architecture consists of two separate ports to access the memory array.

The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations.

Overview

CY7C1241V18 CY7C1256V18 CY7C1243V18 CY7C1245V18 36-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.

Key Features

Separate independent read and write data ports.
Supports concurrent transactions.
300 MHz to 375 MHz clock for high bandwidth.
4-Word Burst for reducing address bus frequency.
Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 750 MHz) at 375 MHz.
Read latency of 2.0 clock cycles.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Echo clocks (CQ and CQ).

More Datasheets from Cypress (now Infineon)

Part Number	Description
CY7C12411KV18	36-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C1241KV18	36-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C12431KV18	36-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C1243KV18	36-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C1243V18	36-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C12451KV18	36-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C1245KV18	36-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C1248KV18	36-Mbit DDR II+ SRAM Two-Word Burst Architecture
CY7C1212F	1-Mbit (64K x 18) Pipelined Sync SRAM
CY7C1212H	1-Mbit (64K x 18) Pipelined Sync SRAM