CY7C1241V18 - 36-Mbit QDR-II SRAM 4-Word Burst Architecture

Product Overview

Cypress Semiconductor

Datasheet Details

Part number	CY7C1241V18
Manufacturer	Cypress Semiconductor
File Size	Direct Link
Description	36-Mbit QDR-II SRAM 4-Word Burst Architecture
Datasheet	CY7C1241V18 Datasheet
Additional preview pages of the CY7C1241V18 datasheet.

Product details

Description

The CY7C1241V18, CY7C1256V18, CY7C1243V18, and CY7C1245V18 are 1.8V Synchronous Pipelined SRAMs, equipped with Quad Data Rate-II+ (QDR-II+) architecture.

Features

Separate independent read and write data ports.
Supports concurrent transactions.
300 MHz to 375 MHz clock for high bandwidth.
4-Word Burst for reducing address bus frequency.
Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 750 MHz) at 375 MHz.
Read latency of 2.0 clock cycles.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Echo clocks (CQ and CQ).

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Published: Apr 15, 2011 |