CY7C1219H sram equivalent, 1-mbit (32k x 36) pipelined dcd sync sram.
* Registered inputs and outputs for pipelined operation
* Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state
* 32K × 36-bit .
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The CY7C1219H SRAM integrates 32K x 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input .
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