CY7C1148V18 Overview
The DDR-II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K.
CY7C1148V18 Key Features
- Functional Description
- SRAM uses rising edges only Echo clocks (CQ and CQ) simplify data capture in high-speed systems Data valid pin (QVLD) to
- HSTL inputs and Variable drive HSTL output buffers
- Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)
- Offered in both Pb-free and non Pb-free packages
- 2M x 8
- 2M x 9
- 1M x 18 CY7C1150V18
- 512K x 36
- 198 Champion Court