CY3125
Features h S a at .D w w w
- VHDL (IEEE 1076 and 1164) and Verilog (IEEE 1364) high-level language pilers with the following features
:
- Designs are portable across multiple devices and/or EDA environments
- Facilitates the use of industry-standard simulation and synthesis tools for board and system-level design
- Support for functions and libraries facilitating modular design methodology
- IEEE Standard 1076 and 1164 VHDL synthesis supports:
- Enumerated types
- Operator overloading
- For... Generate statements
- Blocking and non-blocking procedural assignments
- While loops
- Integers
- Several design entry methods support high-level and low-level design descriptions:
- Behavioral VHDL and Verilog (IF.. ELSE; CASE...)
- Boolean
- Structural Verilog and VHDL
DESIGN ENTRY
- Integers
- IEEE Standard 1364 Verilog synthesis supports:
- Reduction and conditional operators
- Designs can include multiple entry methods (but only one HDL language) in a single design.
- Ultra Gen™...
