* Fully integrated phase-locked loop (PLL)
* FailSafe output
* PLL driven by a crystal oscillator that is phase aligned with external reference
* Output .

that require an extended temperature range
* Compatible across industry standard design platforms
* Industry sta.

Reference Input Clock; 8 kHz or 10 to 60 MHz. Clock Output; 8 kHz or high impedance in buffer mode. Frequency Select 1; Determines CLK outputs per Table 1. Frequency Select 2; Determines CLK outputs per Table 1. Voltage Supply; 3.3V. Ground Clock Out.

Since 2006. D4U Semicon.   |   Contact Us   |   Privacy Policy   |   Purchase of parts