Datasheet4U Logo Datasheet4U.com

CY7C340 - Multiple Array Matrix High-Density EPLDs

General Description

The Cypress Multiple Array Matrix (MAX®) family of EPLDs provides a user-configurable, high-density solution to general-purpose logic integration requirements.

With the combination of innovative architecture and state-of-the-art process, the MAX EPLDs offer LSI density without sacrificing speed.

Key Features

  • Erasable, user-configurable CMOS EPLDs capable of implementing high-density custom logic functions.
  • 0.8-micron double-metal CMOS EPROM technology (CY7C34X).
  • Advanced 0.65-micron CMOS technology to increase performance (CY7C34XB).
  • Multiple Array MatriX architecture optimized for speed, density, and straightforward design implementation.
  • Programmable Interconnect Array (PIA) simplifies routing.
  • Flexible macrocells increase utilization.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
CY7C341B 192-Macrocell MAX EPLD Cypress Semiconductor
CY7C344 32-Macrocell MAX EPLD Cypress Semiconductor
CY7C344B 32-Macrocell MAX EPLD Cypress Semiconductor
CY7C346 USE ULTRA37000TM FOR ALL NEW DESIGNS(128-Macrocell MAX EPLD) Cypress Semiconductor
CY7C331 Asynchronous Registered EPLD Cypress Semiconductor

Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C342 128-Macrocell MAX EPLDs
CY7C342B 128-Macrocell MAX EPLDs
CY7C343 64-Macrocell MAX EPLD
CY7C343B 64-Macrocell MAX EPLD
CY7C345 128-Macrocell MAX EPLDs

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
E PL D CY7C340 EPLD Family Multiple Array Matrix High-Density EPLDs Features • Erasable, user-configurable CMOS EPLDs capable of implementing high-density custom logic functions • 0.8-micron double-metal CMOS EPROM technology (CY7C34X) • Advanced 0.65-micron CMOS technology to increase performance (CY7C34XB) • Multiple Array MatriX architecture optimized for speed, density, and straightforward design implementation — Programmable Interconnect Array (PIA) simplifies routing — Flexible macrocells increase utilization — Programmable clock control — Expander product terms implement complex logic functions General Description The Cypress Multiple Array Matrix (MAX®) family of EPLDs provides a user-configurable, high-density solution to general-purpose logic integration requirements.