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CY7C344B - 32-Macrocell MAX EPLD

Description

Available in a 28-pin, 300-mil DIP or windowed J-leaded ceramic chip carrier (HLCC), the CY7C344 represents the Logic Block Diagram [1] 15(22) 15(23) 27(6) 28(7) INPUT INPUT INPUT INPUT INPUT INPUT INPUT 1(8) 13(20) 14(21) INPUT/CLK 2(9) Pin Configurations HLCC Top View I/O I/O I/O VCC GND I/O I/O

Features

  • High-performance, high-density replacement for TTL, 74HC, and custom logic.
  • 32 macrocells, 64 expander product terms in one LAB.
  • 8 dedicated inputs, 16 I/O pins.
  • 0.8-micron double-metal CMOS EPROM technology.
  • 28-pin, 300-mil DIP, cerDIP or 28-pin HLCC, PLCC package densest EPLD of this size. Eight dedicated inputs and 16 bidirectional I/O pins communicate to one logic array block. In the CY7C344 LAB there are 32 macrocells and 64 expander product ter.

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Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C344 32-Macrocell MAX EPLD
CY7C341B 192-Macrocell MAX EPLD
CY7C346 USE ULTRA37000TM FOR ALL NEW DESIGNS(128-Macrocell MAX EPLD)
CY7C331 Asynchronous Registered EPLD
CY7C335 Universal Synchronous EPLD

Full PDF Text Transcription

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USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C344B 32-Macrocell MAX® EPLD Features • High-performance, high-density replacement for TTL, 74HC, and custom logic • 32 macrocells, 64 expander product terms in one LAB • 8 dedicated inputs, 16 I/O pins • 0.8-micron double-metal CMOS EPROM technology • 28-pin, 300-mil DIP, cerDIP or 28-pin HLCC, PLCC package densest EPLD of this size. Eight dedicated inputs and 16 bidirectional I/O pins communicate to one logic array block. In the CY7C344 LAB there are 32 macrocells and 64 expander product terms. When an I/O macrocell is used as an input, two expanders are used to create an input path. Even if all of the I/O pins are driven by macrocell registers, there are still 16 “buried” registers available.
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