CY7C1372CV25 Datasheet | Cypress

CY7C1370CV25 CY7C1372CV25 512K x 36/1M x 18 Pipelined SRAM with No BL™ Architecture Features - Pin-patible and functionally equivalent to ZBT™ - Supports 250-MHz bus operations with zero wait states - Available speed grades are 250, 225, 200 and 167 MHz - Internally self-timed output buffer control to eliminate the need to use asynchronous OE - Fully registered (inputs and outputs) for pipelined operation - Byte Write capability - Single 2.5V power supply - Fast clock-to-output times - 2.6 ns (for 250-MHz device) - 2.8 ns (for 225-MHz device) - 3.0 ns (for 200-MHz device) - 3.4 ns (for 167-MHz device) - Clock Enable (CEN) pin to suspend operation - Synchronous self-timed writes - Available in 100 TQFP, 119 BGA, and 165 f BGA packages - IEEE 1149.1 JTAG Boundary Scan - Burst capability- linear or interleaved burst order - “ZZ” Sleep Mode option and Stop Clock option Functional Description The CY7C1370CV25 and CY7C1372CV25 are 2.5V, 512K x 36 and 1M x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (No BL) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1370CV25 and CY7C1372CV25 are equipped with the advanced (No BL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent Write/Read transitions. The CY7C1370CV25 and CY7C1372CV25 are pin patible and functionally equivalent to ZBT devices. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Write operations are controlled by the Byte Write Selects (BWa- BWd for CY7C1370CV25 and BWa- BWb for CY7C1372CV25) and a...