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CY7C1370CV25 Datasheet

Manufacturer: Cypress (now Infineon)
CY7C1370CV25 datasheet preview

Datasheet Details

Part number CY7C1370CV25
Datasheet CY7C1370CV25_Cypress.pdf
File Size 712.71 KB
Manufacturer Cypress (now Infineon)
Description 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
CY7C1370CV25 page 2 CY7C1370CV25 page 3

CY7C1370CV25 Overview

They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1370CV25 and CY7C1372CV25 are equipped with the advanced (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle.

CY7C1370CV25 Key Features

  • Pin-patible and functionally equivalent to ZBT™
  • Supports 250-MHz bus operations with zero wait states
  • Available speed grades are 250, 225, 200 and 167 MHz
  • Internally self-timed output buffer control to eliminate the need to use asynchronous OE
  • Fully registered (inputs and outputs) for pipelined operation
  • Byte Write capability
  • Single 2.5V power supply
  • Fast clock-to-output times
  • 2.6 ns (for 250-MHz device)
  • 2.8 ns (for 225-MHz device)
Cypress (now Infineon) logo - Manufacturer

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Part Number Description
CY7C1370C 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
CY7C1370D 18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM
CY7C1371C 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture
CY7C1371S 18-Mbit (512K x 36) Flow-Through SRAM
CY7C1372C 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
CY7C1372CV25 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
CY7C1372D 18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM
CY7C1373C 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture
CY7C131AE 1K/2K x 8 Dual-Port Static RAM
CY7C131E 1K/2K x 8 Dual-Port Static RAM

CY7C1370CV25 Distributor

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