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ADN2818 - (ADN2817 / ADN2818) Clock and Data Recovery IC

Download the ADN2818 datasheet PDF. This datasheet also covers the ADN2817 variant, as both devices belong to the same (adn2817 / adn2818) clock and data recovery ic family and are provided as variant models within a single manufacturer datasheet.

Description

The ADN2817/ADN2818 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 12.3 Mb/s to 2.7 Gb/s.

The ADN2817/ADN2818 automatically locks to all data rates without the need for an external reference clock or programming.

Features

  • Serial data input: 12.3 Mb/s to 2.7 Gb/s Exceeds ITU-T Jitter Specifications Integrated Limiting Amp: 6mV sensitivity (ADN2817 only) Adjustable slice level: ±100 mV (ADN2817 only) Patented dual-loop clock recovery architecture Programmable LOS detect (ADN2817 only) Slice level and sample phase adjustments (ADN2817 only) Integrated PRBS Generator and Detector No reference clock required Loss of lock indicator Supports Double Data Rate Relative Bit Error Rate Monitor Rate Selectivity without the u.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (ADN2817_AnalogDevices.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number ADN2818
Manufacturer Analog Devices
File Size 343.29 KB
Description (ADN2817 / ADN2818) Clock and Data Recovery IC
Datasheet download datasheet ADN2818 Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.DataSheet4U.com Continuous Rate 12.3Mb/s to 2.7Gb/s Clock and Data Recovery ICs Preliminary Technical Data FEATURES Serial data input: 12.3 Mb/s to 2.7 Gb/s Exceeds ITU-T Jitter Specifications Integrated Limiting Amp: 6mV sensitivity (ADN2817 only) Adjustable slice level: ±100 mV (ADN2817 only) Patented dual-loop clock recovery architecture Programmable LOS detect (ADN2817 only) Slice level and sample phase adjustments (ADN2817 only) Integrated PRBS Generator and Detector No reference clock required Loss of lock indicator Supports Double Data Rate Relative Bit Error Rate Monitor Rate Selectivity without the use of a reference clock I2C™ interface to access optional features Single-supply operation: 3.
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