AD9551
Description
The AD9551 accepts one or two reference input signals to synthesize one or two output signals. The AD9551 uses a fractional-N PLL that precisely translates the reference frequency to the desired output frequency.
Key Features
- The AD9551 uses an external crystal and an internal DCXO to provide for holdover operation
- If both references fail, the device maintains a steady output signal
- The AD9551 provides pin-selectable, preset divider values for standard (and FEC adjusted) network frequencies
- The pinselectable frequencies include any bination of 15 possible input frequencies and 16 possible output frequencies
- A SPI interface provides further flexibility by making it possible to program almost any rational input/output frequency ratio
- The AD9551 is a clock generator that employs fractional-N-based phase-locked loops (PLL) using sigma-delta (Σ-Δ) modulators (SDMs)
