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Analog Devices Semiconductor Electronic Components Datasheet

AD8304 Datasheet

160 dB Range (100 pA -10 mA) Logarithmic Converter

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AD8304 pdf
a
FEATURES
Optimized for Fiber Optic Photodiode Interfacing
Eight Full Decades of Range
Law Conformance 0.1 dB from 1 nA to 1 mA
Single-Supply Operation (3.0 V– 5.5 V)
Complete and Temperature Stable
Accurate Laser-Trimmed Scaling:
Logarithmic Slope of 10 mV/dB (at VLOG Pin)
Basic Logarithmic Intercept at 100 pA
Easy Adjustment of Slope and Intercept
Output Bandwidth of 10 MHz, 15 V/s Slew Rate
1-, 2-, or 3-Pole Low-Pass Filtering at Output
Miniature 14-Lead Package (TSSOP)
Low Power: ~4.5 mA Quiescent Current (Enabled)
APPLICATIONS
High Accuracy Optical Power Measurement
Wide Range Baseband Log Compression
Versatile Detector for APC Loops
160 dB Range (100 pA –10 mA)
Logarithmic Converter
AD8304
FUNCTIONAL BLOCK DIAGRAM
VPDB
6
VSUM
3
IPD INPT
4
VSUM 5
VPS2
10
PWDN
2
PDB
BIAS
~10k
VPS1
12
AD8304
VREF
7 VREF
0.5V
TEMPERATURE
COMPENSATION
5k
8 VLOG
9 BFIN
13 BFNG
1
VNEG
14
ACOM
11
VOUT
PRODUCT DESCRIPTION
The AD8304 is a monolithic logarithmic detector optimized for
the measurement of low frequency signal power in fiber optic
systems. It uses an advanced translinear technique to provide an
exceptionally large dynamic range in a versatile and easily used
form. Its wide measurement range and accuracy are achieved
using proprietary design techniques and precise laser trimming.
In most applications only a single positive supply, VP, of 5 V
will be required, but 3.0 V to 5.5 V can be used, and certain
applications benefit from the added use of a negative supply,
VN. When using low supply voltages, the log slope is readily
altered to fit the available span. The low quiescent current and
chip disable features facilitate use in battery-operated applications.
The input current, IPD, flows in the collector of an optimally
scaled NPN transistor, connected in a feedback path around a
low offset JFET amplifier. The current-summing input node
operates at a constant voltage, independent of current, with a
default value of 0.5 V; this may be adjusted over a wide range,
including ground or below, using an optional negative supply.
An adaptive biasing scheme is provided for reducing the dark
current at very low light input levels. The voltage at Pin VPDB
applies approximately 0.1 V across the diode for IPD = 100 pA,
rising linearly with current to 2.0 V of net bias at IPD = 10 mA.
The input pin INPT is flanked by the guard pins VSUM that
track the voltage at the summing node to minimize leakage.
The default value of the logarithmic slope at the output VLOG is
accurately scaled to 10 mV/dB (200 mV/decade). The resistance
at this output is laser-trimmed to 5 k, allowing the slope to be
lowered by shunting it with an external resistance; the addition
of a capacitor at this pin provides a simple low-pass filter. The
intermediate voltage VLOG is buffered in an output stage that can
swing to within about 100 mV of ground (or VN) and the posi-
tive supply, VP, and provides a peak current drive capacity of
± 20 mA. The slope can be increased using the buffer and a pair
of external feedback resistors. An accurate voltage reference of
2 V is also provided to facilitate the repositioning of the intercept.
Many operational modes are possible. For example, low-pass filters
of up to three poles may be implemented, to reduce the output
noise at low input currents. The buffer may also serve as a com-
parator, with or without hysteresis, using the 2 V reference, for
example, in alarm applications. The incremental bandwidth of
a translinear logarithmic amplifier inherently diminishes for small
input currents. At the 1 nA level, the AD8304s bandwidth is
about 2 kHz, but this increases in proportion to IPD up to a
maximum value of 10 MHz.
The AD8304 is available in a 14-lead TSSOP package and specified
for operation from 40°C to +85°C.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002


Analog Devices Semiconductor Electronic Components Datasheet

AD8304 Datasheet

160 dB Range (100 pA -10 mA) Logarithmic Converter

No Preview Available !

AD8304 pdf
AD8304–SPECIFICATIONS (VP = 5 V, VN = 0 V, TA = 25؇C, unless otherwise noted.)
Parameter
INPUT INTERFACE
Specified Current Range
Conditions
Pin 4, INPT; Pin 3 and Pin 5, VSUM
Flows toward INPT Pin
Min1
100
Input Node Voltage
Temperature Drift
Input Guard Offset Voltage
PHOTODIODE BIAS2
Minimum Value
Transresistance
Internally preset; may be altered
40°C < TA < +85°C
VIN VSUM
Established between Pin 6, VPDB, and Pin 4
IPD = 100 pA
0.46
20
70
LOGARITHMIC OUTPUT
Slope
Intercept
Law Conformance Error
Maximum Output Voltage
Minimum Output Voltage
Output Resistance
Pin 8, VLOG
Laser-trimmed at 25°C
0°C < TA < 70°C
Laser-trimmed at 25°C
0°C < TA < 70°C
10 nA < IPD < 1 mA, Peak Error
1 nA < IPD < 1 mA, Peak Error
Limited by VN = 0 V
Laser-trimmed at 25°C
196
194
60
35
4.95
REFERENCE OUTPUT
Voltage WRT Ground
Output Resistance
Pin 7, VREF
Laser-trimmed at 25°C
40°C < TA < +85°C
1.98
1.92
OUTPUT BUFFER
Input Offset Voltage
Input Bias Current
Incremental Input Resistance
Output Range
Output Resistance
Wide-Band Noise3
Small Signal Bandwidth3
Slew Rate
Pin 9, BFIN; Pin 13, BFNG; Pin 11, VOUT
Flowing out of Pin 9 or Pin 13
20
RL = 1 kto ground
IPD > 1 µA (see Typical Performance Characteristics)
IPD > 1 µA (see Typical Performance Characteristics)
0.2 V to 4.8 V output swing
POWER-DOWN INPUT
Logic Level, HI State
Logic Level, LO State
Pin 2, PWDN
40°C < TA < +85°C, 2.7 V < VP < 5.5 V
40°C < TA < +85°C, 2.7 V < VP < 5.5 V
2
POWER SUPPLY
Positive Supply Voltage
Quiescent Current
In Disabled State
Negative Supply Voltage4
Pin 10 and Pin 12, VPS1 and VPS2; Pin 1, VNEG
3.0
|1VP VN| < 8V
NOTES
1Minimum and maximum specified limits on parameters that are guaranteed but not tested are six sigma values.
2This bias is internally arranged to track the input voltage at INPT; it is not specified relative to ground.
3Output Noise and Incremental Bandwidth are functions of Input Current; see Typical Performance Characteristics.
4Optional
Specications subject to change without notice.
Typ Max1
10
0.5 0.54
0.02
+20
100
200
200 204
207
100 140
175
0.05 0.25
0.1 0.7
1.6
0.1
5 5.05
2 2.02
2.08
2
+20
0.4
35
VP 0.1
0.5
1
10
15
1
5 5.5
4.5 5.3
60
0 5.5
Unit
pA
mA
V
mV/°C
mV
mV
mV/mA
mV/dec
mV/dec
pA
pA
dB
dB
V
V
k
V
V
mV
µA
M
V
µV/Hz
MHz
V/µs
V
V
V
mA
µA
V
–2– REV. A


Part Number AD8304
Description 160 dB Range (100 pA -10 mA) Logarithmic Converter
Maker Analog Devices
Total Page 20 Pages
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