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EP1C20 - FPGA

Download the EP1C20 datasheet PDF. This datasheet also covers the EP1C3 variant, as both devices belong to the same fpga family and are provided as variant models within a single manufacturer datasheet.

General Description

Logic Array Blocks6 Logic Elements 9 MultiTrack Interconnect 17 Embedded Memory23 Global Clock Network & Phase-Locked Loops34 I/O Structure 44 Power Sequencing & Hot Socketing 60 IEEE Std.

Key Features

  • The CycloneTM field programmable gate array family is based on a 1.5-V, 0.13-µm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phaselocked loops (PLLs) for clocking and a dedicated double data rate (DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory requirements, Cyclone devices are a cost-effective solution for data-path.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (EP1C3-Altera.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number EP1C20
Manufacturer Altera
File Size 1.08 MB
Description FPGA
Datasheet download datasheet EP1C20 Datasheet

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Other Datasheets by Altera

Part Number Description
EP1C12 FPGA
EP1C3 FPGA
EP1C4 FPGA
EP1C6 FPGA
EP1800 48-Macrocell EPLD

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
April 2003, ver. 1.2 ® Cyclone FPGA Family Data Sheet Introduction Preliminary Information Features... The CycloneTM field programmable gate array family is based on a 1.5-V, 0.13-µm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phaselocked loops (PLLs) for clocking and a dedicated double data rate (DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory requirements, Cyclone devices are a cost-effective solution for data-path applications. Cyclone devices support various I/O standards, including LVDS at data rates up to 311 megabits per second (Mbps) and 66-MHz, 32-bit peripheral component interconnect (PCI), for interfacing with and supporting ASSP and ASIC devices.