AS7C332MNTF18A sram equivalent, 3.3v 2m x 18 flowthrough sram.
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* Organization: 2,097,152 words × 18 bits NTD™architecture for efficient bus operation Fast clock to data access: 7.5/8.5/10.
requiring random access or read-modify-write operations. NTD™ devices use the memory bus more efficiently by introducing.
The AS7C332MNTF18A family is a high performance CMOS 32 Mbit synchronous Static Random Access Memory (SRAM) organized as 2,097,152 words × 18 bits and incorporates a LATE Write. This variation of the 32Mb+ synchronous SRAM uses the No Turnaround Dela.
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